From: Barry Ma (firstname.lastname@example.org)
Date: Mon Jun 05 2000 - 14:25:08 PDT
Jay, Here is my two cents worth.
(1) We know the article by Clayton Paul, "Effectiveness of multiple decoupling capacitors," (IEEE EMC Vol. 34, p. 130, May 1992). Now this article by Douglas Brooks, “ESR and bypass capacitor self resonant behavior, ” (www.ultracad.com) quite well answered a naturally raised question after Paul’s paper:
“In the past, with large numbers of capacitors spread all over our boards, anti-resonant peaks have not generally been regarded as an issue. How did we get away with that for so long?” – (quoted from the article by Brooks)
(2) In today’s high-speed digital design, if having built good inter plane capacitance with your PCB it might not be compulsory to strictly follow Brook’s article in selecting all decaps, I'm afraid.
On Mon, 05 June 2000, Jay Marano wrote:
I'm looking for any feedback from those who have read the white paper on the Ultracad web site regarding ESR and Bypass self resonant behavior. One of the things it demonstrates is that for a given number of capacitors, better system impedance results are obtained from using more cap values, with moderate but not super low ESR, spread over a range than with a smaller set of cap values, with very low ESR, at well chosen self-resonant frequencies.
I understand the theory behind his analysis, but it raises an interesting question:
In the frequency range between the bulk capacitors and the knee frequency of your system, is it better to purposely use wider tolerance caps and use a smaller number of values, or buy more tighter tolerance values and rely on the nominal values to smooth out the system impedance?
Any feedback on this analysis would be appreciated.
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