From: Barry Ma (email@example.com)
Date: Fri Jun 02 2000 - 15:44:32 PDT
We don't know what is the highest frequency your project has to treat. If you guys "Thought about buried capacitance", it seems that you wanted to use interplane capacitance to deal with that frequency. There two techniques for plane cap:
(1) Standard Laminates. The plane spacing can be controlled to 4 - 10 mils.
(2) Buried Capacitance (BC). The spacing can reach to 2 mils.
If you are not ready for BC, you may consider the stackup of adjacent pwr/gnd planes to apply ordinary plane cap.
No matter what plane-cap technique you apply, the number of bypass caps can be reduced, and you don't have to be anxious about the precious real estate on your PCB.
My 2 cents.
On Fri, 02 June 2000, firstname.lastname@example.org wrote:
> I'll second what Barry said, and add, most any bypassing scheme lends
> itself to using buried capacitive layers. If you were to just add the
> capacitive layers to your existing "power" planes, which may or may not
> be in close proximity to the "ground" planes, you'd enjoy the added
> capacitance value and probably some decrease in noise.
> References will be provided if required.
> ---------Included Message----------
> > Date: 2 Jun 2000 10:22:40 -0700
> > From: "Barry Ma" <email@example.com>
> > Reply-To: "Barry Ma" <firstname.lastname@example.org>
> > To: <email@example.com>
> > Cc: <firstname.lastname@example.org>
> > Subject: [SI-LIST] : Re: [SI-LIST] Bypassing of large fpga's
> > Bill,
> > I cannot understand what you said: "Thought about buried capacitance, but our
> > power plane scheme doesn't lend itself to that." ... I don't think it's a good
> > idea to separate the pwr and gnd planes. ...
> > Regards,
> > Barry Ma
> > bma@ANRITSU.com
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