RE: [SI-LIST] : Board Stackup - again ...

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From: Moran, Brian P (brian.p.moran@intel.com)
Date: Fri Jun 02 2000 - 12:57:11 PDT


Doug,

Most high layer count designs I have done use dual stripline pairs between
power and ground layers. Its nice if you happen to get power and ground
adjacent but its hard to guarantee, es[ecially when you have multiple
voltages. One option I have used is to have a standard 12 layer with no
adjacent planes and then build a version using BC (buried capacitance)
pwr/gnd pairs in place of the normal pwr plane positions. This makes it a
14 layer stack but the BC spacing is only 2 mils so you get good high
frequency decoupling without blowing out the stack dimensions.

Brian P. Moran

Intel Corporation
Platform Design Engineering
brian.p.moran@intel.com
(916) 356-1912

-----Original Message-----
From: Doug McKean [mailto:dmckean@corp.auspex.com]
Sent: Friday, June 02, 2000 11:25 AM
To: SI - List Discussion Group
Subject: [SI-LIST] : Board Stackup - again ...

What are the opinions of separating power and
ground planes with a signal layer?

Is it a *hard fast rule* that never shall they be separated?
Are there some caveats conditions that allow separation?

Assuming that everything except stackup remains the same,
is there some significant measurable difference with say
a digital board handling clocks around 40 MHz to 80 MHz
and bus speeds of say PCI, and fsb of 133 (maybe even 200)
and/or Ethernet with power and ground planes separated with
a signal layer as opposed to one that has them adjacent?

I've been of the opinion that power and ground planes should
NEVER be separated, but lately, I'm not so sure about that.

Comments?

- Doug McKean

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