From: [email protected]
Date: Thu Jun 01 2000 - 17:15:27 PDT
I'm currently placing a board with many tightly spaced 676 pin Xilinx BGA's
(XCV600's). Per Xilinx they are claiming one bypass for each power pin, which
adds up to about 76 caps. This eats huge amounts of via sites for routing. We're
currently using a .1uF 0603. Have looked at 0402's but they seem hard to find.
Also considered the 0508 IDC cap from AVX which has much lower inductance in the
hopes of reducing component count. The problem with the IDC's are the fact that
with 8 leads, you need a fanout with 8 vias which ends up eating as much space
as you saved by reducing part count. AVX says it's about a 2 or 3 to 1 tradeoff
(1 IDC is the equivalent to 2 to 3 0603 X7R's).
Thought about buried capacitance, but our power plane scheme doesn't lend itself
to that.
Thinking of placing a cap on both sides at the same location, and using via in
pad to connect the pairs together.
We're currently at 16 layers with the following stack.
Top
POWER (Maybe split with core and I/O voltage)
S
GND
S
S
GND
S
S
GND
S
S
GND
S
POWER
Bottom
Any other thoughts on how to effectively bypass these large devices, while
conserving via sites.
Any help much appreciated.
Bill McGiffin
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