Re: [SI-LIST] : Selection of Characteristic Impedance - regarding

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From: selvaraj subramanian (selvaraj.manian@wipro.com)
Date: Wed May 31 2000 - 23:13:41 PDT


Hi brian,

thanks for your info..

Selva

----- Original Message -----
From: Moran, Brian P <brian.p.moran@intel.com>
To: 'selvaraj subramanian ' <selvaraj.manian@wipro.com>
Cc: <si-list@silab.eng.sun.com>
Sent: Wednesday, May 31, 2000 9:16 PM
Subject: RE: [SI-LIST] : Selection of Characteristic Impedance - regarding

> Selva,
>
> There were alot of very good and detailed answers to a similiar question
> posed just a few weeks back. Here is one perspective. The optimal
> characteristic impedance is a function of several variables, most noteably
> the driver characteristics, and PCB material and geometry limitations.
Most
> logic families are designed to run between 50 & 100 ohms, skewed to the
> lower end. Most controlled impedance connectors tend to be 50 to 75 ohms.
> Typical multilayer FR-4 board stacks, optimized for routing density and
> coupling control, run around 50 to 65 ohms. Therefore the vast majority
of
> designs use 50 to 65 ohms as nominal impedance. This results in 4/4 or
5/5
> trace geometries on standard 4 to 5 mil dielectrics. Striplines are
usually
> groups in orthogonal pairs at 4/4/4, or 5/5/5, or something similiar.
> Playing into this is also the fact that it is good coupling control
strategy
> to keep the height above the reference plane less than the edge to edge
> spacing, as a minimum. The higher the impedance the greater the height
>
> One advantage of higher impedance is lower capacitive loading and the
> drivers output impedance doesn't have as great an impact on the waveform,
> through series termination effects, on multi-drop interconnects. On the
> other hand, lower impedance traces are more heavily capacitive, and
> therefore, non-uniform capacitive loading doesn't create as large of
> discontinuities along the line. This is why RAMBUS is run at 28 ohms.
> There are other issues which I'm sure people will point out. This is my
> opinion in a nutshell.
>
>
> Brian P. Moran
>
> Intel Corporation
> Platform Design Engineering
> brian.p.moran@intel.com
> (916) 356-1912
>
>
>
> -----Original Message-----
> From: selvaraj subramanian [mailto:selvaraj.manian@wipro.com]
> Sent: Wednesday, May 31, 2000 1:41 AM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Selection of Characteristic Impedance - regarding
>
>
> Hello,
>
> I am little bit confused in selecting the characteristic impedance of a
> trace.
>
> How can I select the Zo of a trace for a particular application? Does it
> depends upon the frequency of the signal flowing through the trace?
> Does it depends upon the driver capability?
>
> Let me know how to decide upon Zo of a trace for an application. What are
> the parameters I have to consider before deciding Zo of a trace?
>
> If you have any information or application note, you can send it to me.
That
> will be very helpful to me.
>
> thanks and regards,
> Selva
>
>
>
>
>
>
>
>
>
>
>
>
> ************************************************************
> S. SELVARAJ
> Senior Engineer - VLSI/System Design - Global R&D Solutions
> Wipro Technologies
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>
>
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