RE: [SI-LIST] : Selection of Characteristic Impedance - regarding

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From: Moran, Brian P ([email protected])
Date: Wed May 31 2000 - 08:46:03 PDT

There were alot of very good and detailed answers to a similiar question
posed just a few weeks back. Here is one perspective. The optimal
characteristic impedance is a function of several variables, most noteably
the driver characteristics, and PCB material and geometry limitations. Most
logic families are designed to run between 50 & 100 ohms, skewed to the
lower end. Most controlled impedance connectors tend to be 50 to 75 ohms.
Typical multilayer FR-4 board stacks, optimized for routing density and
coupling control, run around 50 to 65 ohms. Therefore the vast majority of
designs use 50 to 65 ohms as nominal impedance. This results in 4/4 or 5/5
trace geometries on standard 4 to 5 mil dielectrics. Striplines are usually
groups in orthogonal pairs at 4/4/4, or 5/5/5, or something similiar.
Playing into this is also the fact that it is good coupling control strategy
to keep the height above the reference plane less than the edge to edge
spacing, as a minimum. The higher the impedance the greater the height
One advantage of higher impedance is lower capacitive loading and the
drivers output impedance doesn't have as great an impact on the waveform,
through series termination effects, on multi-drop interconnects. On the
other hand, lower impedance traces are more heavily capacitive, and
therefore, non-uniform capacitive loading doesn't create as large of
discontinuities along the line. This is why RAMBUS is run at 28 ohms.
There are other issues which I'm sure people will point out. This is my
opinion in a nutshell.

Brian P. Moran

Intel Corporation
Platform Design Engineering
[email protected]
(916) 356-1912


-----Original Message-----
From: selvaraj subramanian [mailto:[email protected]]
Sent: Wednesday, May 31, 2000 1:41 AM
To: [email protected]
Subject: [SI-LIST] : Selection of Characteristic Impedance - regarding

I am little bit confused in selecting the characteristic impedance of a
How can I select the Zo of a trace for a particular application? Does it
depends upon the frequency of the signal flowing through the trace?
Does it depends upon the driver capability?
Let me know how to decide upon Zo of a trace for an application. What are
the parameters I have to consider before deciding Zo of a trace?
If you have any information or application note, you can send it to me. That
will be very helpful to me.
thanks and regards,
Senior Engineer - VLSI/System Design - Global R&D Solutions
Wipro Technologies
"Samrudhi Bhavan"
37, Castle Street
Ashok Nagar
Bangalore-560 025, India
Tel: 91-80-5367297/98 Ext:115
Fax: 91-80-5576032
E-mail: [email protected] <mailto:[email protected]> <>
The World's First SEI CMM Level 5 Software Services Company

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