Re: [SI-LIST] : Split Plane

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From: Doug McKean (dmckean@corp.auspex.com)
Date: Wed May 24 2000 - 10:49:17 PDT


Just some ideas I thought I might mention.
I'm sure you're probably well aware.

A 100 MHz signal with a 400ps edge *might* not be
that slow.

First, don't know what the requirements of the clock
are but if the need is a nice crisp signal, something
like the 7th harmonic may be needed. That brings you
out to 700 MHz before the a half power point.

Second, the board must be have a bandwidth out to
something like 750 MHz in order to allow a 400 ps
edge to exist.

So the 100 MHz digital board might end up like a
700 - 800 MHz analog board.

If by chance this is a critical design and your board
vendor is board testing only up to 1 MHz at the fab
house (you'd have to check on this), then you *might*
want to consider some extra check of the board. Not
sure what that would be.

At a former company, we noticed a 3dB difference in
signal level from one side of the board to the other
during normal runs. That was unacceptable due to FCC
req.'s of CATV signals and ended up with a complete
respin of the board. First release boards ended up
being very expensive.

Don't mean to complicate things. Just thought
an extra 2 cents might be worth while.

Regards, Doug McKean

Brad Crowell wrote:
>
> Short answer...
>
> Around 0.4ns
>
> Brad

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