From: Scott McMorrow ([email protected])
Date: Wed May 24 2000 - 10:08:19 PDT
Actually the model is correct. Most likely it is being used incorrectly
in the simulator.
The PIII processor uses AGTL+ (assisted GTL+) driver. The assisted
part is a p-channel "kicker" stage to help rising edge performance.
Since the bus is "open-collector" in principal this output stage is
designed to emulate open collector behavior after the first cycle.
The p-channel driver is fired on the first cycle of a multicycle burst
and is then disable. This is the behavior which should be
replicated in the [Driver Schedule] Section of the IBIS model.
Since this is and IBIS 3.2 feature and not all simulators can
use Version 3.2 models with the Driver Schedule section, the
IBIS model must support version 2.1 simulators also, for backwards
compatability. As a result, the main body of the model indicates
that it is open collector. This is correct, since it is the closest
IBIS 2.1 approximation to the actual behavior of this buffer. The
Driver Schedule section is just ignored.
However, with an IBIS 3.2 capable simulator the Driver Schedule
section for the p-channel will provide the proper control of the
output, turning it on at the beginning of the cycle and then
turning it off 10 ns later for a 100 MHz bus (or 7.5ns later for
a 133 MHz bus). This may not be well documented in the
model or in the Intel literature. Basically the buffer should turn
off at the end of one full clock cycle.
Most likely the turn off delay in the model is incorrect for the
bus speed you are simulating, or the simulator is incorrectly
using this model.
-- Scott McMorrow Principal Engineer SiQual, Signal Quality Engineering 18735 SW Boones Ferry Road Tualatin, OR 97062-3090 (503) 885-1231 http://www.siqual.com
"Richard A. Schumacher" wrote:
> Welcome to the wonderful world of IBIS model verification. > > regards, > Richard Schumacher > Hewlett Packard Company > > > > Dear SI gurus: > > Recently, we found one very strange, but interesting thing, i.e. we > > used some open-drain devices for AGTL+ signal integrity simulation, but we > > got such surprising phenomena between simulation and measurement. So here, > > we'd like to ask your great help to clarify and solve our questions on > > open-drain feature (Please see my below questions in detail.), and how to > > define its IBIS model exactly and properly. > > (1) From our understanding about open-drain concept, it's in high-Z stage > > for P-MOS when L->H transition, meanwhile, it also uses pull-up voltage to > > drive out. My question is does it really stay "High-Z" stage and no current > > go through its "power-clamp" diode?? > > (2) From our measurement result, we get an obvious rignback after rising > > edge for open-drain device. But we don't get this from our simulation tool. > > So we check our open-drain model and find that it defines "L->H" V/I curve > > for P-MOS, not using "High-Z" definition. So we modify it as "High-Z" > > condition and obtain the similar result to measurement after re-simulating. > > We also check Intel's models, such as CPU model which also defines "L->H" > > V/I curve for P-MOS. Do you think which one is right, the "High-Z" or > > existing "L->H" V/I curve for P-MOS?? Why?? Does any one know why the IBIS > > model defines the "L->H" V/I curve instead of "High-Z" for open-drain device > > with "Driver Schedule" keyword, at least Intel did it in their models. > > (PS. Intel uses "Driver Schedule" keyword in IBIS model in order to let > > P-MOS turn on/off by a little bit timing delay. But I don't understand why > > its P-MOS has V/I curve for "Driver Schedule", but "High-Z" for general > > open-drain definition??) > > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > [email protected] In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****
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