Re: [SI-LIST] : SI simulation issue for open-drain device

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From: Richard A. Schumacher (schumach@valencia.rsn.hp.com)
Date: Wed May 24 2000 - 06:43:47 PDT


Welcome to the wonderful world of IBIS model verification.

regards,
Richard Schumacher
Hewlett Packard Company

 
> Dear SI gurus:
> Recently, we found one very strange, but interesting thing, i.e. we
> used some open-drain devices for AGTL+ signal integrity simulation, but we
> got such surprising phenomena between simulation and measurement. So here,
> we'd like to ask your great help to clarify and solve our questions on
> open-drain feature (Please see my below questions in detail.), and how to
> define its IBIS model exactly and properly.
> (1) From our understanding about open-drain concept, it's in high-Z stage
> for P-MOS when L->H transition, meanwhile, it also uses pull-up voltage to
> drive out. My question is does it really stay "High-Z" stage and no current
> go through its "power-clamp" diode??
> (2) From our measurement result, we get an obvious rignback after rising
> edge for open-drain device. But we don't get this from our simulation tool.
> So we check our open-drain model and find that it defines "L->H" V/I curve
> for P-MOS, not using "High-Z" definition. So we modify it as "High-Z"
> condition and obtain the similar result to measurement after re-simulating.
> We also check Intel's models, such as CPU model which also defines "L->H"
> V/I curve for P-MOS. Do you think which one is right, the "High-Z" or
> existing "L->H" V/I curve for P-MOS?? Why?? Does any one know why the IBIS
> model defines the "L->H" V/I curve instead of "High-Z" for open-drain device
> with "Driver Schedule" keyword, at least Intel did it in their models.
> (PS. Intel uses "Driver Schedule" keyword in IBIS model in order to let
> P-MOS turn on/off by a little bit timing delay. But I don't understand why
> its P-MOS has V/I curve for "Driver Schedule", but "High-Z" for general
> open-drain definition??)
>

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