RE: [SI-LIST] : Split Plane

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From: Brad Crowell ([email protected])
Date: Wed May 24 2000 - 05:30:40 PDT


Short answer...

Around 0.4ns

Brad

> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of Doug McKean
> Sent: Tuesday, May 23, 2000 6:22 PM
> To: [email protected]
> Subject: Re: [SI-LIST] : Split Plane
>
>
> Short question ...
>
> What's the fastest edge rate?
>
> - Doug
>
> Brad Crowell wrote:
> >
> > Michael and others who have replied,
> >
> > Yes, we have included alot of ground on this board. The concern
> for EMC/EMI
> > issues is quite high for our client, this is for a medical
> application. We
> > pulled out all the stops to ensure every signal layer is referenced to a
> > ground plane, rather than a power plane, which I understand should give
> > better EMC performance. We are also trying to avoid routing on the outer
> > layers as much as possible. The stackup you attached to your
> reply would not
> > provide as much interplane capacitive coupling, which concerns me. Clock
> > rates on my board are about 100MHz max, not extremely fast but
> includes some
> > devices with pretty quick edges.
> >
> > Thanks for all the comments,
> > Brad
>
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