Re: [SI-LIST] : Differential Clock Signal Pair

About this list Date view Thread view Subject view Author view

From: Scott McMorrow (scott@vasthorizons.com)
Date: Mon May 22 2000 - 02:18:51 PDT


Steve,

The assumption here is that the dielectric is homogeneous for both
signals of a pair routed the same length in different geographic
areas. This assumption is false for FR4 in particular.
(The dielectric constant of FR4 as seen by a trace is highly dependent
upon the orientation of the trace over fiberglass bundles and the direction
of the "grain". Since fiberglass is porous, the water content of different areas
of the board varies. This variation can cause large differences in Er and
the accompanying velocity of propagation.) It is more
likely that the dielectric can be considered homogeneous for tightly
coupled side-by-side differential pairs than it can for weakly coupled
differential pairs. It is generally most homogeneous for broadside
differential pairs, however, manufacturing tolerance issues preclude
their use ... except for those who have the time and money to
control the manufacturing process.

Otherwise ...
weak coupling will subject the pair to susceptability from other
coupling sources. This coupling will cause differential skew.
This differential skew can be decomposed into a differential
component and a common mode component. The net effect is
that differential skew due to either mis-matched trace velocities
or additional coupling sources will cause voltage jitter in
the received signal at the differential crossing. This jitter has the effect
of reducing the CMRR of the system. Not to mention that it
looks "yucky" on an eye diagram.

Recently, we have worked with drivers that exhibit a launched edge
rate of 110 ps into the center of a 50 ohm line. It only takes 60 ps of differential
skew to never see a differenial crossing, no matter what the source
of that skew is ... whether driver
                             ... or unmatched lines
                                 ... or outside non-symmetric coupling source
                                     ... or receiver.

Any skew causes reduction in receiver voltage margins and causes
eye closure.

I think I'll place my best design bets on tight coupling of side-to-side
differential pairs with large gaps (3X or more) from one set of differential pairs
to another.

I happen to enjoy good clean differential crossings.

best regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

"S. Weir" wrote:

> Jim, > > How do you propose to get the differential coupling much above 15% so as to > make the differential coupling dominant over the single-ended coupling? > > I agree with your point that it is delay matching that we want, but I think > that with certain reasonably valid assumptions, Lee's assertion that > matched length realizes matched delay holds. Given that it would be very > naive to either mix a stripline and microstrip, or use unequal single-ended > impedances on the pair, aside from etching tolerances, the velocities will > be equal. > > Regards, > > Steve. > At 02:00 PM 5/19/2000 -0700, you wrote: > >You need to generalize length matching to flight time matching for this > >to > >be true. If two differential signals have matched length but differ > >only > >in their spacings to the ground plane which is their signal return plane > >then > >the two signals will have different propagation velocities and hence > >different flight times even though their physical lengths are matched. > > > >The easiest way to match the propagation velocities is to have the two > >signals tightly coupled. > > > >The tight coupling will dominate over the coupling to other conductors > >in the PCB. So this dominate tight coupling will determine the > >propagation > >velocity instead of the coupling to other conductors. The dominate > >tight > >coupling is inherently balanced between the two signals, hence the > >propagation velocities are inherently balanced. The same cannot be said > >for > >two independently routed signals. > > > >Also the variations in the PCB will usually affect both signals equally > >and > >hence equally affect their propagation velocities. > > > >Jim > > > >Ritchey Lee wrote: > > > > > > Differential signalling doesn't by definition, or any other rule, depend on > > > tight coupling for proper operation. Length matching is the only > > parameter that > > > really counts. Sure, you need to make sure that noise doesn't couple > > into the > > > pair differentially. Sid by side routing does not guarantee that on a > > PCB. On > > > the contrary, side by side routing in a PCB will aslways result in > > differential > > > noise coupling. > > > > > > Common mode noise coupling only occurs when the field strength of the > > inducing > > > signal is the same in both wires. This cannot occur in a PCB when the > > inducer > > > is on the same layer as the pair. > > > > > > Lee > > > > > > Weston Beal wrote: > > > > > > > Brian, > > > > > > > > By definition, differential signals should be tightly coupled. This > > implies > > > > close spacing. This does not necessarily mean that the seperation > > should be > > > > minimized. You need to do some analysis to decide the stackup, > > width, and > > > > space that creates the differential impedance that is correct for your > > > > design. > > > > > > > > Regards, > > > > Weston > > > > > > > > -----Original Message----- > > > > From: owner-si-list@silab.eng.sun.com > > > > [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Brian Seol > > > > Sent: Monday, May 15, 2000 9:38 AM > > > > To: si-list@silab.eng.sun.com > > > > Subject: [SI-LIST] : Differential Clock Signal Pair > > > > > > > > Hi everyone, > > > > > > > > I have a simple question about trace layout design for a differential > > clock > > > > signal pair of high-speed CMOS memory packages. I have two design > > > > guidelines for that as follows: > > > > > > > > 1. SPACING between a differential clock signal trace pair must be > > > > MINIMIZED as well as matched in length in order to reduce noise. > > > > > > > > 2. Differential clock signal trace pair must be matched in length in > > order > > > > to achieve matched electrical characteristics, but SPACING between > > > > them must be MAXIMIZED in order to reduce crosstalk noise. > > > > > > > > Which do you prefer? > > > > > > > > Thanks and regards, > > > > > > > > Brian > > > >**** To unsubscribe from si-list or si-list-digest: send e-mail to > >majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > >si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > >si-list archives are accessible at http://www.qsl.net/wb6tpu > >**** > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:26 PST