From: Greim, Michael ([email protected])
Date: Sun May 21 2000 - 04:25:49 PDT
Hi Brad,
Let me see if I can help out. My first thought is
that you have alot of ground on this board. You
also have two power planes coupling to each other.
In the absence of how this stackup was arrived at
and your board thickness requirements, I will offer
some advice.
On a properly decoupled board, the signal does
not always have to run next to a ground or the
power plane that it is referenced to. It appears that
you are trying to run your signals next to only the
ground planes.
Here is a stackup that we have used with great
success up to toggle rates of 100 Mhz. Signals
have a local ground and you end up with 2 additional
routing layers. Make sure that your copper weights
are adequate for your needs, but I think this should
do the trick. The board also fits into a 0.0625
thickness with out any exotic thin core materials.
As you can see, the impedance from layer to layer
is very consistent.
I hope that this helps out.
<<pcilk_r1_stk.doc>>
Best Regards,
Michael Greim
And all this science they don't understand
It's just my job six days a week.....
The time is gone, The email's over, thought I'd
something more to say.........
Michael C. Greim Consulting Engineer
Mercury Computer Systems, Inc email: [email protected]
199 Riverneck Road V: 978-256-0052/x1607
Chelmsford, MA 01824-2820 F: 978-256-4778
> -----Original Message-----
> From: Brad Crowell [SMTP:[email protected]]
> Sent: Friday, May 19, 2000 5:05 PM
> To: [email protected]
> Subject: [SI-LIST] : Split Plane
>
> I have been lurking in the shadows of the SI list for some time now, but
> have come across a situation that I could use some advice on:
>
> I am working on a board design that is using the following stackup:
>
> 1 - SIGNAL
> 2 - GROUND
> 3 - SIGNAL
> 4 - SIGNAL
> 5 - GROUND
> 6 - 5V PLANE
> 7 - 3.3V PLANE
> 8 - GROUND
> 9 - SIGNAL
> 10- SIGNAL
> 11- GROUND
> 12- SIGNAL
>
> My problem is that we are running out of routing resources. Thus,
> it has been suggested that a few traces could be routed on layer 6,
> the 5v plane. The intent would be to route some traces for the 3.3v
> devices which are located away from the 5v devices on the board. This
> would reduce the effect of any splits in the plane. Also, since there
> is a ground plane available as a reference for every signal layer,
> a split in a supply plane shouldn't have much effect, if any. I am
> inclined to think, with my limited SI experience, that this should
> be ok, but would appreciate comments from some of the experts.
>
>
> Thanks,
> Brad
> ***************************************
> Brad Crowell
> Hardware Designer
> AMIRIX Systems
> ***************************************
>
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