Re: [SI-LIST] : Differential Clock Signal Pair

About this list Date view Thread view Subject view Author view

From: Jim McGee ([email protected])
Date: Fri May 19 2000 - 14:00:13 PDT

You need to generalize length matching to flight time matching for this
be true. If two differential signals have matched length but differ
in their spacings to the ground plane which is their signal return plane
the two signals will have different propagation velocities and hence
different flight times even though their physical lengths are matched.

The easiest way to match the propagation velocities is to have the two
signals tightly coupled.

The tight coupling will dominate over the coupling to other conductors
in the PCB. So this dominate tight coupling will determine the
velocity instead of the coupling to other conductors. The dominate
coupling is inherently balanced between the two signals, hence the
propagation velocities are inherently balanced. The same cannot be said
two independently routed signals.

Also the variations in the PCB will usually affect both signals equally
hence equally affect their propagation velocities.


Ritchey Lee wrote:
> Differential signalling doesn't by definition, or any other rule, depend on
> tight coupling for proper operation. Length matching is the only parameter that
> really counts. Sure, you need to make sure that noise doesn't couple into the
> pair differentially. Sid by side routing does not guarantee that on a PCB. On
> the contrary, side by side routing in a PCB will aslways result in differential
> noise coupling.
> Common mode noise coupling only occurs when the field strength of the inducing
> signal is the same in both wires. This cannot occur in a PCB when the inducer
> is on the same layer as the pair.
> Lee
> Weston Beal wrote:
> > Brian,
> >
> > By definition, differential signals should be tightly coupled. This implies
> > close spacing. This does not necessarily mean that the seperation should be
> > minimized. You need to do some analysis to decide the stackup, width, and
> > space that creates the differential impedance that is correct for your
> > design.
> >
> > Regards,
> > Weston
> >
> > -----Original Message-----
> > From: [email protected]
> > [mailto:[email protected]]On Behalf Of Brian Seol
> > Sent: Monday, May 15, 2000 9:38 AM
> > To: [email protected]
> > Subject: [SI-LIST] : Differential Clock Signal Pair
> >
> > Hi everyone,
> >
> > I have a simple question about trace layout design for a differential clock
> > signal pair of high-speed CMOS memory packages. I have two design
> > guidelines for that as follows:
> >
> > 1. SPACING between a differential clock signal trace pair must be
> > MINIMIZED as well as matched in length in order to reduce noise.
> >
> > 2. Differential clock signal trace pair must be matched in length in order
> > to achieve matched electrical characteristics, but SPACING between
> > them must be MAXIMIZED in order to reduce crosstalk noise.
> >
> > Which do you prefer?
> >
> > Thanks and regards,
> >
> > Brian

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:25 PST