From: Ron Miller ([email protected])
Date: Fri May 19 2000 - 13:09:20 PDT
Sal
The medium is band limited, and has differing delays
vs frequency component(group delay) which will distort
the eye pattern. This is referred to at pattern dependent
jitter or inter-symbol interferenece(ISI).
This adds to the random jitter
Ron Miller
]
Salvador Aguinaga wrote:
> Ron,
>
> Having read your reply prompts me to ask a question, though I realize it's a
> little off the subject.
>
> If I have a long (18" or any length for this matter) pair of point-to-point
> traces (for differential signalling) and I am no using the physical ICs to drive
> and receive the signal, does it make sense to test for Random or Data-dependent
> jitter when all I have is a random bit pattern generator driving these lines?
>
> Does the medium have an effect on any one type of jitter (random, RMS, etc.)?
> [By "medium" I mean the type of trace topology, impedance control, delay
> mismatch, stripline or microstrip, etc.]
>
> Thanks,
> -- S. Agui
>
> --------------------------------------------------------------------------------
>
> �aga Jr.
>
> Ron Miller <[email protected]> on 05/17/2000 04:08:56 PM
>
> Please respond to [email protected]
>
> Sent by: Ron Miller <[email protected]>
>
> To: "'si-list @silab.eng.sun.com'" <[email protected]>
> cc: (Salvador Aguinaga/MW/US/3Com)
> Subject: RE: [SI-LIST] : Point to Point Timing Budget and BER Calculations
>
> --------------------------------------------------------------------------------
>
> Tony
>
> I cannot agree with your precept that we cannot simulate random jitter.
>
> NOISE ANALYSIS
> One of the biggest contributors is thermal noise which varys the voltage
> amplitude, so at the crossover it causes jitter in the waveform. Shot noise
> and similar noise sources as well as assumed EMI received on traces can
> be estimated and added to thermal noise. I think HSPICE has a means to
> add this in. ADS does for sure.
>
> OTHER RANDOM JITTER SOURCES
> The clock generator has random jitter but is usually specified as phase
> noise
> and is usually ~10 ps or there about.
> Digital gates can phase modulate the signal edge, but this is usually quite
> small and is caused by amplitude variations in the ICs caused again by noise
> and also by crosstalk with other signals at the gate levels.
>
> These are all secondary effects and are small. Random noise is the big
> culprit
> in random jitter, and can be simulated.
>
> Ron Miller
>
> > -----Original Message-----
> > From: Tony Sweeney
> > Sent: Wednesday, May 17, 2000 10:16 AM
> > To: [email protected]
> > Subject: [SI-LIST] : Point to Point Timing Budget and BER
> > Calculations
> >
> >
> > I have been working on several point to point applications using various
> > buffers and over various transmission line length. HPSPICE is being used
> > to model:
> >
> > Output Buffer
> > Bondwires (coupled)
> > Package Model (coupled)
> > Board Vias (lumped)
> > Transmission line (W model coupled)
> > Board Vias
> > Package
> > Bondwires
> > Input Buffer
> >
> > On chip power distribution is modeled for a group of outputs for SSO
> > analysis
> > A seperate clock path is also modeled and simulated with the data
> > Simulations are run over process, volatage and temp corners.
> >
> > Different pattern sets are used to evaluate SSO, and Crosstalk. The
> > cross talk pattern is modified with the middle trace getting an Pseudo
> > Random Pattern. ISI is measured at the far end.
> >
> > In the end, eye patterns are generated and we can see the margin in
> > setup and hold times.
> >
> > The question is: Given we cannot simulate Random Jitter, how much margin
> > do you need to garuntee a very low BER? Can you mathmatically predict
> > BER based on a deterministic Jitter Budget?
> >
> > If you have very small margin let's say 10ps with your deterministic
> > budget, does that mean you will have a high BER?
> >
> >
> > --
> > Anthony C. Sweeney
> > Field Applications Engineer
> > LSI Logic Corporation
> > 7585 Ronson Road
> > San Diego, CA 92111
> > Ph: 858-467-6980
> > Fax: 858-496-0548
> > Pager: 888-961-7562
> >
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> >
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--
Ronald B. Miller _\\|//_ Signal Integrity Engineer
(408)487-8017 (' 0-0 ') fax(408)487-8017
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[email protected], [email protected]
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