Date: Wed May 17 2000 - 20:50:42 PDT
You ask an open question, so the open answer to that is "it depends." It
depends on how much current the IC is drawing, what frequency and rise time
it has, what type of load the IC output drivers are driving, how much noise
on the power plane the other ICs on the same board can tolerate . . . . You
are looking for a solution that will work in every case, but you will find
that there are problems or exceptions to every solution. A capacitor stores
charges and supplies current to ICs when needed. By that definition, the
charges on the capacitor must move in phase from each other. For parallel
plates to behave as a good capacitor, their dimensions should be much
smaller than a wavelength so the charges on the plates will move in phase.
Large parallel plates behave as transmission lines. A quarter wavelength
transmission line with a short at the end has infinite impedance, so
capacitors placed 1/4 wavelength away are bad. This means that we can
loosely define the largest usable board area capacitance as 1/8 wavelength
radius of copper surrounding the IC power pin. Charges stored on the planes
further than 1/8 wavelength away are not very usable due to the time delay.
At 500MHz in FR4, 1/8 wavelength is 1.5 inches. Is such a board capacitor
good enough for your IC? It might be if you have a CMOS IC driving another
CMOS IC less than 2 inches away, so the load on the output of the 1st IC is
mainly the CMOS gate capacitance at the input of the 2nd IC at the end of
the 2 inch transmission line. During switching, the 2nd IC draws current
from the output of the 1st IC for the 1st 200 or 300 ps to charge up the
input gate capacitance on the 2nd IC. The current is an impulse function,
although the voltage waveform is a step function. If these ICs are small
and uses little power, the board capacitance might be enough to supply the
impulse current for the 1st IC. If the load on the transmission line is a
termination resistor, the current draw will be a step function, and the
board capacitance alone may not be good enough. But here is an exception.
You have a board that uses only CMOS devices, and the largest IC is a 500
MHz processor that consumes 50W of power at 2.5v, so it switches 20A of
current at 500 MHz. It is a CMOS device, so its current draws are mostly
impulse functions. Would the board capacitance be good enough for this 20A
switching current? Probably not. Making the pwr plane larger will not
help, but using more layers in parallel will help. You might have to use 4,
8, or 16 pwr/gnd layer pairs in parallel for this board, the more layers the
better. But wait!! Isn't that what a multilayer ceramic capacitor is? It
has many pwr/gnd layers in parallel . . . . Hmmmmmm, if we could only take
advantage of that . . . I'm thinking that if you have to use a 50W, 500MHz
processor, and your boss tells you that you cannot have 8 pwr/gnd layers on
your board, you or someone will probably find a way to make the ceramic
capacitor work effectively beyond 1 GHz!! Another question you might ask is
that "do I really want to dump the 20A switching noise directly into the
pwr/gnd planes and create pwr/gnd bounce and board resonance to interfere
with all the ICs on the board, not to mention EMI problems?
From: Barry Ma [mailto:email@example.com]
Sent: Monday, May 15, 2000 1:33 PM
To: George_Tang@exchange.dell.com; firstname.lastname@example.org
Subject: RE: Charge moving from decoupling capacitors
Thanks a lot for your inputs.
All responses to my second question are only concerned with the inductance
due to “long” distance between chip and decap. Nobody seems to agree
imposing another constrain to the distance. My question was
“Do we really have to limit the distance letting the charge have enough time
to move from the cap to the chip during the rise time interval? I doubt it.”
But I really read an article implying this extra concern.
George, you wrote:
> This is true if you have only DC current. For AC, you may have water in
the pipe but
> no water out of the faucet if the faucet is switching out of phase from
the water in
> the pipe.
Thank you for reminding me of Frequency Domain analysis. Yes, I should have
described and analyzed a transient problem (charge travel during Tr) in both
TD and FD, and then correlate the results. Let me have a try this time:
It is generally acknowledged that decaps and plane cap are complementary
(supposing a 10 mil or less spacing between pwr and gnd planes). Decaps
cover low end of frequency range, while the plane cap takes care of high
frequencies. Thus the interplane cap would play more and more important role
in high-speed PCB design, as the speed gets faster and faster. On the other
hand, nobody objects closer distances from decaps to the chip, if possible.
..... When a chip drains necessary charges from pwr/gnd planes during Tr,
decaps would supply charges to pwr and gnd planes on lower frequencies,
while interplane cap can respond itself on higher frequencies.
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