From: Dima Smolyansky (email@example.com)
Date: Wed May 17 2000 - 17:06:50 PDT
Would you classify the pattern-dependent jitter, which results from
crosstalk between the lines and even-odd mode delay variability, as part of
your overall jitter in the system? That can definitely be simulated if one
as a dependable model of coupling between the lines.
TDA Systems, Inc.
11140 SW Barbur Blvd., Suite 100
Portland, OR 97219
(503) 246-2282 (fax)
(503) 804-7171 (mobile)
----- Original Message -----
From: Ron Miller <rmiller@Brocade.COM>
Sent: Wednesday, May 17, 2000 2:08 PM
Subject: RE: [SI-LIST] : Point to Point Timing Budget and BER Calculations
> I cannot agree with your precept that we cannot simulate random jitter.
> NOISE ANALYSIS
> One of the biggest contributors is thermal noise which varys the voltage
> amplitude, so at the crossover it causes jitter in the waveform. Shot
> and similar noise sources as well as assumed EMI received on traces can
> be estimated and added to thermal noise. I think HSPICE has a means to
> add this in. ADS does for sure.
> OTHER RANDOM JITTER SOURCES
> The clock generator has random jitter but is usually specified as phase
> and is usually ~10 ps or there about.
> Digital gates can phase modulate the signal edge, but this is usually
> small and is caused by amplitude variations in the ICs caused again by
> and also by crosstalk with other signals at the gate levels.
> These are all secondary effects and are small. Random noise is the big
> in random jitter, and can be simulated.
> Ron Miller
> > -----Original Message-----
> > From: Tony Sweeney
> > Sent: Wednesday, May 17, 2000 10:16 AM
> > To: firstname.lastname@example.org.Sun.COM
> > Subject: [SI-LIST] : Point to Point Timing Budget and BER
> > Calculations
> > I have been working on several point to point applications using various
> > buffers and over various transmission line length. HPSPICE is being used
> > to model:
> > Output Buffer
> > Bondwires (coupled)
> > Package Model (coupled)
> > Board Vias (lumped)
> > Transmission line (W model coupled)
> > Board Vias
> > Package
> > Bondwires
> > Input Buffer
> > On chip power distribution is modeled for a group of outputs for SSO
> > analysis
> > A seperate clock path is also modeled and simulated with the data
> > Simulations are run over process, volatage and temp corners.
> > Different pattern sets are used to evaluate SSO, and Crosstalk. The
> > cross talk pattern is modified with the middle trace getting an Pseudo
> > Random Pattern. ISI is measured at the far end.
> > In the end, eye patterns are generated and we can see the margin in
> > setup and hold times.
> > The question is: Given we cannot simulate Random Jitter, how much margin
> > do you need to garuntee a very low BER? Can you mathmatically predict
> > BER based on a deterministic Jitter Budget?
> > If you have very small margin let's say 10ps with your deterministic
> > budget, does that mean you will have a high BER?
> > --
> > Anthony C. Sweeney
> > Field Applications Engineer
> > LSI Logic Corporation
> > 7585 Ronson Road
> > San Diego, CA 92111
> > Ph: 858-467-6980
> > Fax: 858-496-0548
> > Pager: 888-961-7562
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