[SI-LIST] : RE: Charge moving from decoupling capacitors

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From: Mark Gill (gillmf@nortelnetworks.com)
Date: Wed May 17 2000 - 12:58:29 PDT


Barry -

Dr. Todd Hubing at UMR (others as well) has done some research in this
area.

Recalling some of his published findings, in general terms, with a large
power/ground spacing, the location of the decaps is more important, due
to the inductance associated with the power and ground planes. With
closely spaced power/ground planes, placement of the decaps becomes less
critical. In between these two areas is a transition zone. Given this,
it would seem that power/ground planes and decaps are more complementary
in the transition zone, but not as much so at the boundaries. Note
there are many opinions on this entire subject (decoupling), and most
are backed by extensive research.

My preference is to look at rules as guides, as I have seen far to many
rules broken (sometimes intentionally), still have designs pass EMC with
good margin, and satisfy the concerns of the Signal Integrity engineers.
Everything is relative. If physical designers implemented every EMC
rule on every design, a great deal of cost and delay would be added to
development cycles.

But I will say, experience is the best rule!

Regards,

Mark Gill
EMC/Safety/NEBS Design
Nortel Networks

> -----Original Message-----
> From: Barry Ma [SMTP:barry_ma@altavista.com]
> Sent: Monday, May 15, 2000 4:33 PM
> To: George_Tang@Dell.com; si-list@silab.eng.sun.com
> Cc: emc-pstc@ieee.org
> Subject: RE: Charge moving from decoupling capacitors
>
>
> Thanks a lot for your inputs.
>
> All responses to my second question are only concerned with the inductance
> due to "long" distance between chip and decap. Nobody seems to agree
> imposing another constrain to the distance. My question was
>
> "Do we really have to limit the distance letting the charge have enough
> time to move from the cap to the chip during the rise time interval? I
> doubt it."
>
> But I really read an article implying this extra concern.
>
>
> George, you wrote:
> > This is true if you have only DC current. For AC, you may have water in
> the pipe but
> > no water out of the faucet if the faucet is switching out of phase from
> the water in
> > the pipe.
>
> Thank you for reminding me of Frequency Domain analysis. Yes, I should
> have described and analyzed a transient problem (charge travel during Tr)
> in both TD and FD, and then correlate the results. Let me have a try this
> time:
>
> It is generally acknowledged that decaps and plane cap are complementary
> (supposing a 10 mil or less spacing between pwr and gnd planes). Decaps
> cover low end of frequency range, while the plane cap takes care of high
> frequencies. Thus the interplane cap would play more and more important
> role in high-speed PCB design, as the speed gets faster and faster. On the
> other hand, nobody objects closer distances from decaps to the chip, if
> possible. ..... When a chip drains necessary charges from pwr/gnd planes
> during Tr, decaps would supply charges to pwr and gnd planes on lower
> frequencies, while interplane cap can respond itself on higher
> frequencies.
>
> Best Regards,
> Barry Ma
> bma@ANRITSU.com
>
>
>
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