From: Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Date: Thu May 18 2000 - 14:49:27 PDT
>The decap should be much closer than 0.5 Tr to be of use.
This is the upper limit. Beyond 0.5*Tr (even at 0.5*Tr), the caps would be
totally ineffective within a risetime.
To be effective, there has to be time for the sag to propagate out to the
cap, and time for the replenishing current to propagage back. 2*0.5*Tr =
Tr, meaning the current from the cap wouldn't arrive at the IC until the
very end of the risetime.
>If Tr = 1 ns, the corresponding distance is approximately equal to 14
>cm in FR4. There's no problem to locate decaps much closer than 7 cm,
>following your opinion. If Tr = 0.2 ns (likely happens in 5 - 10 years)
People are already seeing sub- 0.1ns edges from (some) CMOS, depending on
the IC package.
In 5-10 years they could get a lot faster still.
>How did you jump from "capacitors placed 1/4 wavelength away are bad"
>to "the largest usable board area capacitance as 1/8 wavelength
1/4 wavelength is the shortest distance where this effect (ideal caps
looking like an open circuit) happens. The idea is that if you restrict
yourself to about half that, you would avoid that problem; at least for most
digital designs (see below).
>Can I use the same token to infer from "caps placed one wavelength
>away are good" to "the largest usable board area capacitance is
>within 1/2 wavelength radius"? And so, and so on.
No, unless you are working with just RF. Most digital designs operate over
a frequency range from DC to some upper limit. A cap that is one wavelength
away at one frequency, would be 1/4 wavelength away at 1/4 the frequency.
For digital designs, that would be bad.
Sprinkling capacitors over various distances helps partly avoid problems
with capacitors at odd multiples of 1/4 wavelength.
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