From: Tony Sweeney ([email protected])
Date: Wed May 17 2000 - 10:15:34 PDT
I have been working on several point to point applications using various
buffers and over various transmission line length. HPSPICE is being used
to model:
Output Buffer
Bondwires (coupled)
Package Model (coupled)
Board Vias (lumped)
Transmission line (W model coupled)
Board Vias
Package
Bondwires
Input Buffer
On chip power distribution is modeled for a group of outputs for SSO
analysis
A seperate clock path is also modeled and simulated with the data
Simulations are run over process, volatage and temp corners.
Different pattern sets are used to evaluate SSO, and Crosstalk. The
cross talk pattern is modified with the middle trace getting an Pseudo
Random Pattern. ISI is measured at the far end.
In the end, eye patterns are generated and we can see the margin in
setup and hold times.
The question is: Given we cannot simulate Random Jitter, how much margin
do you need to garuntee a very low BER? Can you mathmatically predict
BER based on a deterministic Jitter Budget?
If you have very small margin let's say 10ps with your deterministic
budget, does that mean you will have a high BER?
-- Anthony C. Sweeney Field Applications Engineer LSI Logic Corporation 7585 Ronson Road San Diego, CA 92111 Ph: 858-467-6980 Fax: 858-496-0548 Pager: 888-961-7562**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:21 PST