Date: Mon May 15 2000 - 20:02:01 PDT
In a message dated 5/15/00 1:56:57 PM Pacific Daylight Time,
<< Do you have any controlled experimental measurements to support these
you can share with us? By that I mean before and after measurements
only thing done was to add one structure at a time, such as the chassis
ring or the resonance spoiler capacitors?
There are no individual, one at a time, supporting tests that I have
conducted to prove the singular effectivity of the chassis ground rings
versus some other configuration. My separate response (also sent this day) to
your other question regarding the chassis ground rings and the Faraday cage
effect may offer a partial, qualitative response to whatever is behind your
question. If you need a specific # dB for a set of rings, I can't provide it.
Like much of the work we do, the performance of each design using this
technique will be influenced by the size and shape of the PCB, the slot
width, the clock frequencies and edge rates in the PCB circuits, the nature
of the I/O ports, and the intelligence used in the placement/layout of
circuits in the subassembly. The interaction of these other factors make it
impractical to claim any specific numbers that would assure a PCB designer a
specific level of success were the technique (which does demand PCB real
estate) to be implemented on his/her PCB.
I originally presented the chassis ground ring technique in the HP High-Speed
Design Seminar series over a decade ago. Since then, over 200 different
high-speed designs by companies such as Motorola, Cisco, NetFrame Systems,
Combinet, Xircom, Adaptec, and many others have found extra EMC design margin
using this technique. So far, I have not been made aware of any need for use
of the spoiler capacitors, but I still recommend provisions for mounting them
as a cheap precaution.
Just in case there is some solid doubt in your mind about the usefulness of
the technique, following is an E-mail from one of my repeat clients who
implemented the chassis ground rings along with my other companion
recommendations. The E-mail is doctored in one area for client privacy.
This project was done in February 2000.
I just wanted to pass along an update on the Project A board, now that
the respin of the PCB is complete and I've just completed a new scan at
the EMC labs.
Whereas our best reading was -3dB below class B and getting worse
(higher) from that point, the board now exhibits excellent EMI
characteristics; our worst reading is now -19dB below class B margin and
goes down to -30dB at the best. At most points, the test tech was just
recording noise so that there would be something on the form.
Thank you for your excellent suggestions and for giving us some
additional education on EMC; I feel we will be able to apply this
knowledge to all of our products across the board with similar results.
Our next pass through the test lab will be the "XXXX" board (that was the
little 3" x 5" board), and I will be going back for a full certification
run on the Project A board.
Thanks again. I hope all is going well with you.>>
That's all folks,
Michael L. Conn
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