From: Tom Dagostino ([email protected])
Date: Fri May 12 2000 - 13:47:01 PDT
The answer is, it depends.
If you are looking at modern random logic parts it may make
sense to do just that. Most vendors design a few buffers that
get cut and pasted over the whole family from what I have seen.
For more complex parts I would be very carefull. I know of
one ASIC vendor who has about 500 buffers for one process.
Experience has shown that even in a family of microproccessors,
the buffers are not the same from version to version.
Tom Dagostino
ICX Modeling Group
[email protected]
503-685-1613
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Kim Helliwell
Sent: Friday, May 12, 2000 10:20 AM
To: [email protected]
Subject: [SI-LIST] : Piecing together IBIS models
This has been bothering me for a while. Many vendors who supply
IBIS models on their web pages only provide a few from any
given family. What I'd like to know is: is it appropriate
to use buffer models from existing models in the family to
create new signal models for the same family? I cannot see
anything wrong with this as an approximation, but at least
one vendor has stated to me that it's not a good idea for their
models, at any rate.
If it's not appropriate, are there good reasons why not? Why
would doing this be worse than using the (usually execrable)
default models in my SI tool, for example?
Does anyone else follow this sort of procedure? Do you
take a flying guess at pin parasitics or leave them blank
or copy them from the existing models also?
-- Kim Helliwell Senior CAE Engineer Acuson Corporation Phone: 650 694 5030 FAX: 650 943 7260**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
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