RE: [SI-LIST] : Piecing together IBIS models

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From: Zabinski, Patrick J. (zabinski.patrick@mayo.edu)
Date: Fri May 12 2000 - 13:36:05 PDT


Kim,

I've done this exact thing several times. However, when doing
so, I do my best to verify a few things:

        * Same *exact* package
        * Same I/O family
        * Same fabrication facility and process

Under these conditions, I've used models from one part in
a family for another part in the same family.

I've been told there are several reasons for being cautious:

        * some parts have different package parasitics
        within the same package, so you need to be sure
        you're using the right parasitics

        * if you're trying to model a relatively new
        part within a family (say, based on 0.18 um CMOS)
        buy only have IBIS models for a relative old
        part (say, 0.25 or 0.35 um CMOS), the two do
        not correlate well

        * some vendors don't like to release, support, or
        even suggest using models that haven't been put
        through the ringer (which I believe is the
        correct default approach; although some common-
        sense should prevail if you're dealing with the
        engineering side of the house)

        * several parts (e.g., FPGAs) have different styles
        of packages within a given family, so the package
        models will likely be off

Given the choice of no (zero) model versus an approximate
model, I generally use the approximation.

Pat

>
> This has been bothering me for a while. Many vendors who supply
> IBIS models on their web pages only provide a few from any
> given family. What I'd like to know is: is it appropriate
> to use buffer models from existing models in the family to
> create new signal models for the same family? I cannot see
> anything wrong with this as an approximation, but at least
> one vendor has stated to me that it's not a good idea for their
> models, at any rate.
>
> If it's not appropriate, are there good reasons why not? Why
> would doing this be worse than using the (usually execrable)
> default models in my SI tool, for example?
>
> Does anyone else follow this sort of procedure? Do you
> take a flying guess at pin parasitics or leave them blank
> or copy them from the existing models also?
>
>
> --
> Kim Helliwell
> Senior CAE Engineer
> Acuson Corporation
> Phone: 650 694 5030 FAX: 650 943 7260
>

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