Re: [SI-LIST] : Reducing Power and Ground Noise

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From: Chris Padilla (cpad@cisco.com)
Date: Thu May 11 2000 - 08:18:54 PDT


Hi Steve,

I have to disagree with your second sentence. On one board that was
was being debugged, we found out that we were driving a clock right
into the ground plane of our board! This resulted in a radiation
failure of over 13 dB at a particular frequency. Upon scoping the
clock line, we found the clock drving right around 0 V! This was only
one line of a clock buffer (it was driving 5 or 6 other loads) that
was series terminated. We were amazed the driver was still working
and that the other clocks were humming along just fine. I would have
to guess that the line was about 9 total inches long and the midway
point marked the point of ground entry. So at least in our case, one
single net killed us!

----->Chris

At 03:46 PM, you wrote:
>David,
>
>First, please be sure that your measurement is not lying to you. Things
>have got to be really, really bad if you can reliably see your clock riding
>on the power supply. It is very hard for a single net to do this. It is
>more likely that all the signals triggered by that clock are contributing
>to the problem, and / or your are getting crosstalk between your scope
>channels due to the test set-up. So, if you only address the clock, you
>probably won't correct your symptom as measured.
>
>Even assuming that the measurement is real, and that this one clock signal
>is the source of your troubles, I don't think your proposal is a very good
>idea. If you successfully isolate the power pin input, the signal current
>still has to flow through the signal trace itself through the load and back
>through the power / ground plane structure. Isolating one end makes that
>return path more of a problem, not less.
>
>It sounds like your problem is some combination of:
>
> 1. Inadequate power / ground decoupling, and
> 2. Excessive return path inductance for the high edge rate signals.
>
>Bulk capacitance is good for audio frequencies up to around 1 MHz,
>depending on what type of capacitors you are using. It is unlikely that
>increasing bulk capacitance will help at 64MHz.
>
>On a four layer, .062 board, you are going to be hard pressed to see a
>mounted resonant frequency on the .1 uF decoupling capacitors above 8
>MHz. Either use enough smaller capacitors, or lots of .1's to get the
>impedance down.
>
>Regards,
>
>
>Steve.
>
>At 09:12 AM 5/10/00 -0400, you wrote:
>>Hi All,
>> I'm working on a board currently which has "high" power and ground
>>noise. I'm looking for effective methods of reducing this noise.
>>
>>I spent a bit of time making power and ground noise voltage measurement on
>>the current configuration of this board. The results show that the power
>>and ground system have noise spikes which are 180 deg. out of phase from an
>>output clock on the board. I won't go into the measurement set up too much,
>>but here are the basics:
>>Using two FET probes to make the measurements. The ground reference was the
>>digital ground input to the board. Scope was triggered off the suspect
>>clock (64Mhz) .
>>
>>I suspect that an input filter to the device generating the signal (an ASIC)
>>would improve things. I'm not sure about the correct configuration for this
>>filter. Currently there are .1uF caps across each of the input power pin.
>>I can think of two configurations that may be effective.
>>A ferrite bead in series with each of the input power connections (keeping
>>the .1uF caps) may be effective but I'm not sure what "side effects" may
>>occur.
>>A inductor and resistor in parallel (also keeping the .1uF caps) setting the
>>values .75uH and 5 ohms.
>>I'm not sure what the draw backs of these configurations are. Or is there
>>are better solutions.
>>
>>Additionally, I plan on decreasing the power and ground spacing (the board
>>is a four layer) to 7mils, increasing the bulk capacitance to the board, and
>>possibly placing .001uF caps in parallel with each of the .1uF caps.
>>
>>Any comments would be appreciated
>>
>>Best regards
>>
>>David Spencer
>>
>>
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