Re: [SI-LIST] : Match of differential pairs

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From: Heiko Dudek (heikod@cadence.com)
Date: Wed May 10 2000 - 12:34:32 PDT


Martyn,

the impedance of a differential net is determined by the single line impedances
(which depend on the distance to the reference plane, the dielectric material
in-between and the trace width) and the coupling across the two single line traces.

It has been discussed in this forum quite some times, so very briefly:

The differential voltage is formed by Vdiff = Vnoninv - Vinv.

Looking at Ohm's law for a two-port
 
|Vnoninv| |Z11 Z12| |Inoninv|
| | = | |.| |
|Vinv | |Z21 Z22| |Iinv |

calculates the diff impedance to (Z11-Z22)-(-Z12+Z22). Assuming a symmetric setup
(Z11=Z22 and Z12=Z21), this can be reduced to 2*(Z11-Z12).

So every change in the diff pair spacing / diff pair length matching changes the coupling
and therefore the diff pair impedance. Of course, every impedance discontinuity causes
reflection. Besides having a negative effect on EMI as well as xtalk susceptibility, your
timing budgeting might get screwed. For common clock designs, it's just like for single
line nets:

Tflightmax < Clock Period - Driver(Tcomax) - Skew - Jitter - Crosstalk - Receiver(Setup)
Tflightmin > Receiver(Hold) - Driver(Tcomin) + Skew + Jitter + Crosstalk

The only difference is that you have to do first switch and final settle delay measurements
on the differential signal (using, of course, differential thresholds) rather than on the
single line signals. (Be careful that you compensate with differential buffer delay.)

(FirstSwitchDelay is the time the signal crosses Vinput_low at the receiver for the first
time - compensated for the buffer delay - and FinalSettleDelay is the time the signal crosses
Vinput_high the last time at the receiver - again, compensated for the buffer delay.)

Since you doing the measurements on >DiffDriver-DiffTLine(s)-DiffReceiver<, a change in
the differential impedance would change the first switch and final settle delay you get.

So, basically the answer how good your diff pair mates should match comes down to: as long
as the FirstSwitchDelay on your DiffSignal vs DiffThreshold is not less than Tflightmin (from
above equation) and your FinalSettleDelay on your DiffSignal vs DiffThreshold is not more
than Tflightmax, you're fine. However, Tflightmin and Tflightmax depend on your driver /
receiver technology, Tco (clock-to-output), clock skew, clock jitter, clock rate, ...

Regards,
Heiko

At 11:46 PM 5/9/00 +0100, you wrote:
>Hi everyone,
>
>Can anyone help on the following subject? My customers
>are in the PCB manufacturing industry and are increasingly
>called to build differential striplines, however on fine line
>boards it is very hard to make an exact match of the signal
>pair.
>
>This obviously has effects on cmrr, emc etc, but I cannot find
>any documents that define how much mismatch is acceptable on
>a differential pair.
>
>National have a good app note on LVDS for example but when
>matching is discussed it simply says good match is necessary.
>
>This was easy on 7 or 8 mil line width, much less so at 3 to 4 mil.
>
>Look forward to your input
>
>Kind regards
>Martyn Gaudion
>martyn.gaudion@polar.co.uk
>www.polarinst.com
>
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    Heiko Dudek
    Technical Marketing Manager | High Speed Systems Design & IC Packaging
    Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
    
    ph: (978) 262-6384
    fx: (978) 446-6798
    email: heikod@cadence.com

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