From: Mike Saunders (email@example.com)
Date: Wed May 10 2000 - 11:30:00 PDT
Some comments regarding allowable differential pair mismatch:
1. Placing the diff. pairs on the stripline layer is a good selection
since control of line width is easier to maintain on internal layers.
2. Manufacturing deviations should average out (concerning trace width)
along the length of the line. Therefore, by maintaining consistent
spacing, the slight impedance fluctuations along the line should be minimal.
3. What the National app. note does not say specifically is that for
differential pairs, a good match consists of several elements: consistent
trace width/spacing, equal number of vias (if any), trace length matching
(including trace segments which are defined by via transistions), keeping
the overall trace length as short as possible and routing over a continuous
plane when possible. If all of these guidelines are followed, common mode
noise should be minimal.
4. The actual trace length matching tolerance depends on your timing
budget. Usually I try to increase overall desing margin where it is easily
maintained, so I will generally specify a trace length mismatch of +/- 10
MILs maximum. Since flight time is about 1nS per 6" of trace, a 0.010"
mismatch in overall trace length should only produce a mismatch at the
receiver of around 1.6pS. This minimal amount of skew should be within
most timing budgets. Otherwise, specify a tighter mismatch tolerance.
**It is more important to match the trace lengths than to maintain
consistent trace widths or trace spacing.**
5. I don't know what your exact impedance requirements are, but an example
using USB diff. pairs would be as follows:
Target diff. Zo: 90ohms
Single trace Zo: ~45 - 50 ohms
Required stackup & trace specs to meet these requirements: 4 MIL trace
using 2 oz. Cu, 6 MIL space,
4 MIL dielectric height above 2 oz. Cu.
First, specify your trace width, then adjust the dielectric height and Cu
thickness to get the correct single-ended impedance.
Then, adjust the trace spacing to give the target differential impedance.
6. If your stackup allows it, try to keep the trace-to-trace seperation
smaller than the dielectric height. This will do wonders for common mode
noise rejection, as each trace will specifically reference its pair rather
than the plane.
7. Favor shorter and fatter traces if real estate area allows it. This
will cut down on both trace capacitance and trace inductance.
8. Maintain sufficient spacing between the diff. pairs and any other
signal groups, especially clocks and other high-speed signals. Also, keep
diff. pairs at least 2h away from any board edges or apertures.
Hope some of this helps...
At 11:46 PM 5/9/2000 +0100, you wrote:
>Can anyone help on the following subject? My customers
>are in the PCB manufacturing industry and are increasingly
>called to build differential striplines, however on fine line
>boards it is very hard to make an exact match of the signal
>This obviously has effects on cmrr, emc etc, but I cannot find
>any documents that define how much mismatch is acceptable on
>a differential pair.
>National have a good app note on LVDS for example but when
>matching is discussed it simply says good match is necessary.
>This was easy on 7 or 8 mil line width, much less so at 3 to 4 mil.
>Look forward to your input
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