[SI-LIST] : Reducing Power and Ground Noise

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From: Spencer, David H (David.Spencer@usa.xerox.com)
Date: Wed May 10 2000 - 06:12:01 PDT

Hi All,
        I'm working on a board currently which has "high" power and ground
noise. I'm looking for effective methods of reducing this noise.

I spent a bit of time making power and ground noise voltage measurement on
the current configuration of this board. The results show that the power
and ground system have noise spikes which are 180 deg. out of phase from an
output clock on the board. I won't go into the measurement set up too much,
but here are the basics:
Using two FET probes to make the measurements. The ground reference was the
digital ground input to the board. Scope was triggered off the suspect
clock (64Mhz) .

I suspect that an input filter to the device generating the signal (an ASIC)
would improve things. I'm not sure about the correct configuration for this
filter. Currently there are .1uF caps across each of the input power pin.
I can think of two configurations that may be effective.
A ferrite bead in series with each of the input power connections (keeping
the .1uF caps) may be effective but I'm not sure what "side effects" may
A inductor and resistor in parallel (also keeping the .1uF caps) setting the
values .75uH and 5 ohms.
I'm not sure what the draw backs of these configurations are. Or is there
are better solutions.

Additionally, I plan on decreasing the power and ground spacing (the board
is a four layer) to 7mils, increasing the bulk capacitance to the board, and
possibly placing .001uF caps in parallel with each of the .1uF caps.

Any comments would be appreciated

Best regards

David Spencer

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