From: Richard A. Schumacher (email@example.com)
Date: Mon May 08 2000 - 08:29:15 PDT
If you have not already done so, you should also post
to the newsgroup comp.lang.verilog .
> This may be the wrong list to post this to,
> but I haven't found anything better.
> If this post is out of line please redirect me.
> I recently attend a talk by Harry Foster on
> verifiable RTL design.
> Harry suggest using a subset of the verilog language
> to make RTL design more verifiable.
> The idea is similar to synthesis, where only a
> subset of the language is synthesizable.
> He inspired me to look for an extensible "lint"
> program for verilog.
> So what I am looking for is something similar to
> Verilint but in the Free/shareware category.
> Does anybody know of such a thing?
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