From: Moran, Brian P ([email protected])
Date: Mon May 01 2000 - 15:02:05 PDT
Mike,
I spent a fair amount of time researching this issue while at a previous
company. I had a 10 bit wide, 2GHz bus coming out of a PAROLI device into a
SERDES. The clock was embedded on one bit so I was worried about skew
across the bus and maintaining as much of the bandwidth as possible. We went
out to the fifth harmonic. At a distance of 6" to 9" the loss was getting
unacceptable with FR-4. We were looking at GETEK with GORE Speedboard N
prepreg. The low loss, low Er pre-preg allowed for wider traces without
dropping impedance too low, which helpes skin effect losses, as well as
reducing loss tangent. It made the stack up messy because you had to
position your low loss dual striplines in specific layers.
Brian Moran
Intel, Folsom
Signal Integrity Group
>
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