[SI-LIST] : Transient impedance

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From: Sandy Taylor (cmos@rockisland.com)
Date: Tue Nov 16 1999 - 09:58:24 PST


> I'm curious about "smooth break as make" technology. Any earlier papers
> to look at, or will all be revealed in February in SF?
>
> Regards,
> Chris Rode

Hi Chris

When I was at Sun we designed several IO circuits to help push up
the off chip bandwidth. There will be a paper presented in Feb by
Sai Vishwanthaiah (Sun Microsystems) on the subject, including some
schematics and block diagrams. I do not want to take away from
his presentation, but here are some thoughts on how to tackle the problem.

Once you have slew rate control in place on both turn on and turn off
of the pull up and pull down circuits (not just fets!), then it is just a matter
of timing the turn on and turn offs so that as one is turning on the other is
turning off. The desired external slew rate is about an order of magnitude
slower than the internal delays, so there is quite a bit of time to manage the
transition.

The down side of including active analog circuits in the IOs is that you waste
a small amount of power, but this is a very reasonable trade off for the
performance gain.

There is patent information available on controlling the impedance over PVT:
http://patent.womplex.ibm.com/details?pn=US05955894__
which includes references to other impedance control circuits.
Go to the IBM patent search engine:
http://patent.womplex.ibm.com/
and search for "slew rate control" and you will get lots of ideas.

Sandy Taylor
CMOS Solutions

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