From: Bob Perlman (email@example.com)
Date: Mon Nov 15 1999 - 17:03:01 PST
D.C. Sessions wrote:
> As a general rule, we design output stages to keep the crowbar current
> low. Break-before-make, as it were, although it's no exactly sequenced so
> much as just turning off faster than on. Necessarily, though, the output
> goes through a high-impedance point.
> Compounding this is the fact that MOS devices aren't just modulated
> resistors. If the gate-drain voltage is greater than about the threshold
> voltage, then the output is resistive. Otherwise it's more or less a
> constant current, and _that_ is certainly high impedance. As the driver
> turns on or off, you have a situation where the gate-source voltage is
> decreasing while the drain-source voltage is increasing -- the gate-source
> voltage drops REALLY fast, and the transistor spends most of its
> transition time in high impedance.
> Therefore, the high-impedance window for a driver is quite a bit longer
> than the nonoverlap interval. It's very nearly the entire edge time for a
> shunt terminated line, since it starts shortly after the first device
> begins to turn off and only ends when the second finishes turning on.
What are the consequences of this temporarily-high-Z output for
termination? Suppose that I have a 55 ohm clock trace on which
I've placed a 110/110ohm Thevenin termination at the far end, with
the high end tied to 3.3V. Let's further suppose that the driver runs
off 3.3V, and that it's capable of sourcing/sinking 24mA with a
0.4V drop across the P FET or N FET in the steady state.
When the driver is logic HIGH (3.3V - 0.4V = 2.9V) it sources:
(2.9V - 1.65V) / 55 ohms = 22.7mA.
Similarly, it sinks 22.7mA in the LOW state (0.4V).
Now consider what happens when the driver transitions from LOW
to HIGH or HIGH to LOW. If the driver exhibits sufficiently high
impedance during the transition, the drive source current drops to a
low value. Let's suppose, for the sake of argument, that it briefly
drops to zero. The current into the line has changed from +/-
22.7mA to 0. Since the transmission line impedance is 55 ohms,
we launch a voltage wavefront of 22.7mA * 55 ohms = 1.25V down
the line. We'll see a short pedestal at (2.9V-1.25V) = 1.65V (HIGH-
to-LOW transition) or (0.4V + 1.25V) = 1.65V (LOW-to-HIGH
transition). A nice pedestal right in the transition region that lasts
perhaps as long as the risetime/falltime? Yecch!
I'm curious - has anyone ever observed this behavior? I'm not
doubting you, D.C.; quite the contrary. I'm just wondering if this
temporary-high-Z problem has ever manifested itself in an
observable system problem. Or is my analysis oversimplified to
the point that it doesn't describe what actually happens?
Cambrian Design Works
Digital design and signal integrity consulting
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