RE: [SI-LIST] : Assistance with Quad model..

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From: Marc Humphreys (mhumphreys@nexabit.com)
Date: Mon Nov 15 1999 - 06:28:27 PST


Charles,

The other feedback you've got so far should provide a useable solution,
however,
I'd suggest taking advantage of some of the new constructs that were
added to
XTK recently. This way you'll not have to go re-write it in the future
to take
advantage of the new runtime control functions.

You can model it using the new SERIESPIN statement. Beside doing exactly
what you
are trying to do (as per the example) it also supercedes the use of the
TO PIN statement
 in model files. The main reason for using SERIESPIN is that it allows
you to take
advantage of the new runtime controll features added to XTK which allow
you to controll
the state of your gate at runtime. Check out chapter 7-63 in the March
1999 User manual.

You can actually model the analog behavior of the gate to accurately
simulate the
use of such gate in a logic level translation application by
controlloing the gate voltage.
This is modelled using a loadspec
model that includes, VI curve data and the addtional VOLTAGE_CONTROLLED
statement.
Take a look at section 7.6.2 in the March 1999 manual. If you can get an
IBIS model from the
vendor the ibis2xtk translator can create the model for you.

Marc

---------------------------------------------------------------------
Marc Humphreys
Lucent Technologies
Core Routing - InterNetworking Systems
508-460-3355 x236
e-mail: marchumphreys@lucent.com
--------------------------------------------------------------------

 

> -----Original Message-----
> From: Phares, Charles [SMTP:charles.c.phares@intel.com]
> Sent: Friday, November 12, 1999 6:34 PM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Assistance with Quad model..
>
> quad users,
>
> I am trying to create a model to use in quad to approximate the "on"
> resistance and pin capacitance of essentially a cmos transmission
> gate.
> ascii schematically it looks like:
>
> in -------------/\/\/\/\/\/\----------------out
> | r
> |
> = = = c
> |
> |
> gnd
>
> I was hoping that it would be as simple as putting the following
> statements
> in a model file:
>
> MODEL R_1
> PIN 1 TYPE RES_VAL TO PIN 2
> PIN 1 TYPE CAP_PAR
> END_MODEL
>
> LOADSPEC RES_VAL
> REFF: 10
>
> LOADSPEC CAP_PAR
> CEFF: 3.5
>
> But, unfortunately, the TOP file only reads the series resistance
> parameter
> and leaves out the cap. I guess it just doesn't like the dual pin
> definition. It doesn't give me an error though.
>
> Can anyone think of a slick way to make this model, using TOPSPEC or
> something like that?
>
> Thanks,
> Charles Phares
>
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