Re: [SI-LIST] : Plane Capacitance

About this list Date view Thread view Subject view Author view

From: Pat Zabinski ([email protected])
Date: Wed Nov 10 1999 - 10:12:46 PST


Here's a theory I've been working on. To some extent, I've been able
to validate portions of it with passive measurements made in the
lab, but it's far too early to say I've got it nailed down.

The theory goes like this: the effective capacitance of power/ground
planes is related to the risetime AND bit period (or transmission
line prop-delay). In essense, for full swing, rail to rail, CMOS-type
output buffers, the planes (and discrete caps) need to provide
charge during the transition period (i.e.,
risetime) *and* for line charge-up (bit period). The charge must
be provided *when* needed, not *after* the fact. With fast
edge rates (let's not define "fast" in this thread), there
is a delay time from when the charge stored
near the far-edges of the board will be able to react; if this
reaction time is delayed enough, then it will not be provided in
sufficient time to do any good.

Based on some simple experiments (both in the lab and in simulation),
it looks like there is a "radius of effectiveness" for buried
plane capacitance. I cannot give you any form of solid numbers
at this time, but for the buffers I'm working with (a key point),
it looks like my effective capacitance is defined within
a radius of about one-tenth a risetime-plus-bit-period from the buffer
(for short traces, the "bit-period" is replaced with "line

Keep in mind, this is to provide a reasonable eye. If you're
really concerned about the edge rate, then you need to narrow
this radius to something like one-tenth the risetime away
from the buffer.

Specific to your problem, I'd say a first-order approximation
is the effective area of capacitance exists within 1/10th
a risetime away from the buffer, and you should be able
use this radius theory for the center, edges, and corners
of the board.

Again, this is very a preliminary theory, and I'm hoping to see
what others have to say on the topic (both pro & con).


> What is the effective area for this type of capacitance? If you have 10"x10"
> planes with one device in the middle, how much of that 100sq" will help
> the device? What if the device is at the edge or corner of the planes?

**** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at ****

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:44 PST