From: Greim, Michael (email@example.com)
Date: Wed Nov 10 1999 - 03:39:36 PST
You're on the right track. This is a technique that I
used back in the old days designing large memory boards.
Depending on your clock frequency, 1/8 th of the clock cycle
may be overkill for this as many current surges are very localized
over a hundred or so pS (your mileage may vary). So check
your characterization data on your parts. I think that you will
be happy with the result. I found that when using a large number
of high current, impulse need devices this worked out well
as long as your timing is still satisfied.
The bounds of Time, Space or Mechanics should never stand
in the way of a perfectly good idea.......
The time is gone, The email's over, thought I'd
something more to say.........
Michael C. Greim Consulting Engineer
Mercury Computer Systems, Inc email: firstname.lastname@example.org
199 Riverneck Road V: 978-256-0052/x1607
Chelmsford, MA 01824-2820 F: 978-256-4778
> -----Original Message-----
> From: Lfresearch@aol.com [SMTP:Lfresearch@aol.com]
> Sent: Tuesday, November 09, 1999 1:31 PM
> To: email@example.com
> Subject: [SI-LIST] : More Micro Noise;-)
> I'm back...
> We have decided to take a look at the spread spectrum concept for one of
> boards, however, a problem still exists for the other...
> This board has one micro feeding 3 DSP's, in the DSP's there are loads of
> registers that change at the same time. So I have very strong spurs...
> Since I can't tolerate clock jitter, but I could tolerate a skewed clock,
> what if I build in say a 1/8th of a clock cycle delay between each big
> current hog. i.e. The micro transitions on the rising edge of the clock,
> rising edge is delayed slightly ( 1/8th ), then it triggers the first DSP
> then delayed again before triggering the 2nd DSP and so on until after the
> 1/3rd it's time for the micro clock to go high.... and so on.
> While it most likely won't affect the radiation from the chips, it should
> reduce the dips on the power planes... Am I way off base here?
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