Re: [SI-LIST] : Definition of Hi-Speed (UC)

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From: D. C. Sessions (dc.sessions@vlsi.com)
Date: Tue Nov 09 1999 - 15:35:54 PST


Lum Wee Mei wrote:
>
> Pardon me for asking this stupid question because I am at a loss of how
> to explain hi-speed to my boss. He thinks that hi-speed is as simple and
> straightforward as resistance = V/I and nothing else. Hi-speed should be
> some circuits that need to operate at xxMHz or more. Anything less than
> xxMhz is not hi-speed.
>
> I would appreciate anyone of you experts out there who can enlighten me
> in a simple and easy to understand definition so that my boss can
> understand.

OK, so I'm late.

My definition has to do with timing margin. Emphasis: margin.
If your critical margin is less than (a few times) the wire delay
then you're in high-speed country.

With regard to clock and other edge-sensitive signals, 'margin' is
the tolerable glitch width.

Note that these rules sortakinda apply to the usual clock-repetition-rate
metric. Slow timing usually means more margin. Slow clocks can go through
low-bandwidth paths that filter narrow glitches. Which won't save you if
you're running a 14.318 MHz clock from one 0.18 micron IC to another.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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