Re: [SI-LIST] : More Micro Noise;-)

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From: D. C. Sessions (dc.sessions@vlsi.com)
Date: Tue Nov 09 1999 - 11:14:55 PST


Lfresearch@aol.com wrote:
>
> I'm back...
>
> We have decided to take a look at the spread spectrum concept for one of the
> boards, however, a problem still exists for the other...
>
> This board has one micro feeding 3 DSP's, in the DSP's there are loads of
> registers that change at the same time. So I have very strong spurs...
>
> Since I can't tolerate clock jitter, but I could tolerate a skewed clock,
> what if I build in say a 1/8th of a clock cycle delay between each big
> current hog. i.e. The micro transitions on the rising edge of the clock, this
> rising edge is delayed slightly ( 1/8th ), then it triggers the first DSP
> then delayed again before triggering the 2nd DSP and so on until after the
> 1/3rd it's time for the micro clock to go high.... and so on.
>
> While it most likely won't affect the radiation from the chips, it should
> reduce the dips on the power planes... Am I way off base here?

It's a good idea. I'd change it in one regard, though, by not using the
same phase interval between all of the parts. That way you can also reduce
the inphase harmonics as well. (Obviously a bit of math is in order
depending on the number of devices you're using.)

For static logic the #1 power transient comes from the clock buffers in
the flip-flops themselves, and although there's usually some difference
in the magnitude between the rising and falling clock edges it's not
large thanks to the several stages of inversion. Therefore, you don't
get much benefit from using opposite clock edges. Quadrature would be
OK, aside from piling up energy in the even harmonics (CMOS has some odd
-- or perhaps I should say even -- harmonic content.)

I'd have a look at the spectral distribution of your emissions and plan
the phasing to avoid the peaks you already have.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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