[SI-LIST] : More Micro Noise;-)

About this list Date view Thread view Subject view Author view

From: Lfresearch@aol.com
Date: Tue Nov 09 1999 - 10:30:35 PST


I'm back...

We have decided to take a look at the spread spectrum concept for one of the
boards, however, a problem still exists for the other...

This board has one micro feeding 3 DSP's, in the DSP's there are loads of
registers that change at the same time. So I have very strong spurs...

Since I can't tolerate clock jitter, but I could tolerate a skewed clock,
what if I build in say a 1/8th of a clock cycle delay between each big
current hog. i.e. The micro transitions on the rising edge of the clock, this
rising edge is delayed slightly ( 1/8th ), then it triggers the first DSP
then delayed again before triggering the 2nd DSP and so on until after the
1/3rd it's time for the micro clock to go high.... and so on.

While it most likely won't affect the radiation from the chips, it should
reduce the dips on the power planes... Am I way off base here?

Thoughts?

Derek.

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:43 PST