RE: [SI-LIST] : Micro Noise

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From: Zhang, Michael T (michael.t.zhang@intel.com)
Date: Mon Nov 08 1999 - 16:31:24 PST


When spread spectrum is enabled, basically PLLs are trying to catching up a
slowly modulated host clock. How slow? The modulation frequency is typically
around 30kHz. Comparing that to the 100MHz host bus frequency, you would
have over 3000 bus cycles in one modulation period. The clocks are not
modulated by much (~0.5%). So the peak-to-peak period change is small
(roughly 0.5%*10ns = 50ps), which takes about 1500 cycles to complete. Thus,
the consecutive edge variation is extremely small (50ps/1500 = 33fs).

Most PLLs can track such slowly modulated clocks with small spread amount
and don't require any knowledge of the modulation scheme (or so called
"modulation profile").

-Michael T. Zhang
PMD/PPD, Intel Corp
(503)264-2301

-----Original Message-----
From: rbmccammon@mmm.com [mailto:rbmccammon@mmm.com]
Sent: Monday, November 08, 1999 10:57 AM
To: si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Micro Noise

Michael T. Zhang wrote:
One such example is Intel's BX-based motherboards have the optional spread
spectrum clocking feature, which modulates the clocks for processor,
chipset, memory, and PCI, but keeps the USB clock fixed.

Would you elaborate a little bit?

I have this vision of PLL's in different chips chasing
the phase of the clock, but all of them at a different phase
because of different dynamics. Do they all know the modulating
algorithm so they can predict the next phase, or is the rate
of change from one edge to the next held low enough not to be a
problem?

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