Re: [SI-LIST] : RE: Capacitor Inductance

About this list Date view Thread view Subject view Author view

From: Larry Smith (ldsmith@lisboa.eng.sun.com)
Date: Mon Nov 08 1999 - 12:05:38 PST


Michael - Yes, vias in the interdigitated, checkerboard pattern is a
powerful way to reduce inductance. You get the benefit of the mutual
inductance going up to 4 directions from each via.

But this requires the part that you are connecting to the power planes
to also be interdigitated. Some of AVX's Lica capacitors are designed
that way and this is good for inductance. But a standard 0805
capacitor part does not lend itself to interdigitating. You loose more
in the traces than you gain by the interdigitating pattern.

You can still significantly decrease the loop inductance for a standard
0805 capacitor by using multiple vias in parallel, if you are
willing to chew up the wiring channels. My major point was that the
inductance is in the design of the PCB structures. We have to be
willing to make significant consessions at the PCB level before low
inductance capacitors will do any good.

regards,
Larry Smith
Sun Microsystems

> From: MikonCons@aol.com
> Date: Mon, 8 Nov 1999 14:10:12 EST
>
> Larry:
> Regarding your comment...
> <<But in many cases, you could have just put the multiple vias in parallel
> (not in a checkerboard pattern) and mounted a dumb old 0805 capacitor
> on them. There would be almost as much improvement in the inductance
> and you can skip the expensive part. That is because the inductance
> is in the design of the vias, mounting pads and distance to the power
> planes, with only a minor amount attributed to the capacitor.
> >>
>
> One thing you may have overlooked in your commentary about multiple-via pads
> for capacitor mounting is the mutual coupling effect between adjacent +/-
> vias that will reduce inductance much more than paralleling like vias (i.e.,
> all + or all -) in close proximity. The interdigitization (is there such a
> word?) is the basic principal behind the AVX capacitor construction.
>
> Granted, the amount of via inductance reduction may not exceed 50% (which
> only translates to ~40% increase in SRF), but that may be what's needed for a
> leading edge product. Unfortunately, the price tag makes one carefully weigh
> the performance/cost tradeoff.
>
> Michael L. Conn
> Owner/Principal Consultant
> Mikon Consulting

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:42 PST