Re: [SI-LIST] : [Fwd: Majordomo results: Looking for highspeed buffer parts]

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From: Jonathan Dowling (jdowlin2@yahoo.com)
Date: Fri Nov 05 1999 - 20:38:23 PST


Kevin,
Although I am officially allowed to comment only on the
133MHz Coppermine FSB, I have my ears to the wind to
receive any news of portentious consequence and will interrupt
my day of succoring widows and orphans to respond...

The Athlon processor bus is rumored to be point-to-point
with 100MHz strobes clocking on both edges for 200MT/s
performance. No clock/strobe buffering is required.

A fully extracted Athlon processor card model is rumored
to exist in Quad XTK format (ISF). It is most likely
provided as a prenatal service for pregnant OEMs.

Jonathan Dowling

--- Kevin Normoyle <Kevin.Normoyle@eng.sun.com> wrote:
> > > The 240 Mhz part is to buffer the clocks from clock synthesizer
> > >to multiple ASICs as a clock source. The ASICs have 3.3v IO but
> > >are 5V tolerate. I saw and IDT part# IDT74ALVC16244A that may
> > >be promising. Have you had any experience with that part?
> > >
> > > Do you know of any GaAs vendor that may provide faster
> > >parts for my needs? I wonder what people use for buffering
> > >the clocks for AMD's 200 Mhz system clock or DDR clocks?
>
>
> I know jack about designing clocks for AMD athlon system interfaces,
> so I'll comment :) (I'd be interested if others have more info)
>
> But from what I read, the "system clock" is distributed using
> a 100mhz clock? There are strobes for the source synchronous
> interfaces, but if you start fanning those out to multiple parts
> I can't imagine that the existing timing analysis for data vs strobe
> would still be valid?
>
> I would think that AMD has or should be spec'ing what you can or
> can't do.
>
> You're really asking basic questions about the Athlon system interface:
> how it's extended to multiple chips?, and how is clock buffering and
> possible multiple loads on the "bus" signals handled. (at least
> that's what it sounds like).
>
> If so, you may have created a system that is a design point not covered
> by the AMD timing analysis, and you may have some system analysis/design
> to do before you decide how to distribute your strobes/clocks.
>
> I don't know if the Athlon interface is publicly available. It's
> supposed
> to be similar or the same as the early/current DEC Alpha interconnect.
> You might dig up literature referring to Alpha to see how they handled
> the issue. Although I believe they typically interface the CPU to either
> a single controller or bus interface chip also.
>
> I think some of the press about AMD's 200mhz "bus" has been misleading.
> My reading is that it's a point-to-point interconnect protocol. I'm
> interested in whether that's true or not.
>
> Although maybe you're just supposed to be distributing a 100mhz clock
> and using a pll inside your asic to get a 200mhz clock from that?
>
> -kevin
>
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