Re: [SI-LIST] : Micro Noise Part 2

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From: sweir (weirsp@a.crl.com)
Date: Fri Nov 05 1999 - 10:31:38 PST


Derek,

I don't think this is a very good idea:

1. The board is unbalanced and will likely warp.
2. The impedance on the two routing layers will be unequal.

Stick with the original stack-up:

1. The stack-up is balanced.
2. The impedance on both routing layers is matched.
3. The solder layer with most of the routing is adjacent to the ground
reflection plane. This yields the best high frequency performance.
4. The power plane is adjacent to the ground plane which gives you free
buried capacitance, ( although not a lot in a .062 board ),
         which will help with your EMC.

With a four layer board, it is important that you engineer the
placement. Don't toss the netlist over the wall to the layout
folks. Identify your critical nets and account for them in your
placement. Then route the critical nets first.

Regards,

Steve.
At 12:47 PM 11/5/99 -0500, you wrote:
>Hi folks,
>
>first, thanks for the suggestions about what to do with the micro noise.....
>We have some things to try, I'll share what I find out.
>
>One of the things I'd like to try is arranging the PWB layers a little
>differently.
>
>I have a 4 layer board ( I have no say, as usual ), The first design was
>stacked:
>
>Layer 1 Component, Pads, some routing.
>Layer 2 Power
>Layer 3 Ground
>Layer 4 Routing
>
>I'm not keen on this arrangement because traces ( including addres/data etc.
>) are forced to go from layer 1 to 4 to get from A to B. I believe passing
>any trace trough a plane should be avoided if possible...... Even though I'm
>only running a 50 MHz clock! So, what if I do this?:
>
>Layer 1 Component, Pads, some routing.
>Layer 2 Routing
>Layer 3 Ground
>Layer 4 Power
>
>Thoughts why I suggest this:
>
>1) I have to have all parts on the top surface, hence must have pads there.
>2) I have to have some 200 test points on the lower surface, if this were
>ground plane, I'd carve it up big time. I believe that I'd rather have ground
>on Layer 3 and more intact, since the chips can have a decoupling cap sharing
>the power pin pad to make up for crappy power plane.
>3) By making Layer 3 ground, the traces keep closely coupled, faster traces
>will route layer 2 to increase this effect.
>4) The card adjacent to layer 4 is an I/O card, it has Fast Transient Burst
>noise up to 4 kV, and could carry switching noise out on wiring. The
>ground/power layers will help shield layers 1 and 2 from this.
>
>I've not seen this lay-up suggested much, but it looks like it could work. So
>before I go ahead and try it I thought I'd bounce the idea.....
>
>Opinions?
>
>Thanks,
>
>Derek.
>
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