From: Chris Cheng ([email protected])
Date: Fri Nov 05 1999 - 10:25:12 PST
if the sole purpose of the buffer is to drive clocks to ASIC,
why not use LVPECL or differential HSTL fan out buffers. motorola
and synergy semiconductor have lots of LVPECL and differential
HSTL clock buffer. there is no reason why clock inputs has to
be SSTL which is intended for heavy loaded buses not for pt to
pt clock distribution. finally,I think SSTL is a 2.5V standard
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of Jason Zheng
> Sent: Thursday, November 04, 1999 7:18 PM
> To: [email protected]; [email protected]
> Subject: Re: [SI-LIST] : [Fwd: Majordomo results: Looking for highspeed
> buffer parts]
> Thank you very much for the reply!
> The 240 Mhz part is to buffer the clocks from clock synthesizer
> to multiple ASICs as a clock source. The ASICs have 3.3v IO but
> are 5V tolerate. I saw and IDT part# IDT74ALVC16244A that may
> be promising. Have you had any experience with that part?
> Do you know of any GaAs vendor that may provide faster
> parts for my needs? I wonder what people use for buffering
> the clocks for AMD's 200 Mhz system clock or DDR clocks?
> Can you give me a pointer for the GAL part#/vendor info?
> Thanks in advance!
> > From your post, I guess that you want 3.3V SSTTL levels.
> 240MHz is really
> > beyond any practical upper limit for SSTTL. There isn't much
> out there that
> > can reliably get below a Tpd of 1.5nS, which would typically be
> suitable to
> > 150-166MHz at the high-end. If you want to reach beyond 200MHz,
> it is time
> > to use low-swing logic.
> > The application sounds like a phase-splitter. If it is, instead of an
> > inverter try a precision delay line, either buried in etch, or
> off the shelf.
> > The 120MHz mux / FF can be implemented in either a 5nS or 3nS
> GAL. Which
> > grade is appropriate depends on the specifics of your Tsu and Th
> > requirements.
> > Regards,
> > Steve.
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