From: D. C. Sessions ([email protected])
Date: Thu Nov 04 1999 - 19:39:09 PST
Jason Zheng wrote:
> Thank you very much for the reply!
> The 240 Mhz part is to buffer the clocks from clock synthesizer
> to multiple ASICs as a clock source. The ASICs have 3.3v IO but
> are 5V tolerate. I saw and IDT part# IDT74ALVC16244A that may
> be promising. Have you had any experience with that part?
> Do you know of any GaAs vendor that may provide faster
> parts for my needs? I wonder what people use for buffering
> the clocks for AMD's 200 Mhz system clock or DDR clocks?
Urk. You're using this for CLOCKS? At 200+ MHz?
Hate to break the news, but this is going to get ugly.
First off, the net delay through the parts is going to be sneaking up
on your pulse width. The skews are going to be substantial, and
the ground bounce is going to be ugly. All of which wouldn't
be insurmountable except that you're talking about using single-ended
parts in a differential signaling environment.
Nope. Ain't gonna happen.
For DDR clocks at least you can get clock chips made for the job.
Low-skew differential outputs at 2.5v (yes, that's the official
supply) and thirteen or so of them. Work like a charm.
Haven't run the Athlon system bus (but know the guy who did the
original design for DEC). Still, it's a safe bet that it's similar
in its clock setup. You just don't get reliable edge timing at
those speeds from single-ended clocks.
> > From your post, I guess that you want 3.3V SSTTL levels. 240MHz is really
> > beyond any practical upper limit for SSTTL. There isn't much out there that
> > can reliably get below a Tpd of 1.5nS, which would typically be suitable to
> > 150-166MHz at the high-end. If you want to reach beyond 200MHz, it is time
> > to use low-swing logic.
> > The application sounds like a phase-splitter. If it is, instead of an
> > inverter try a precision delay line, either buried in etch, or off the shelf.
> > The 120MHz mux / FF can be implemented in either a 5nS or 3nS GAL. Which
> > grade is appropriate depends on the specifics of your Tsu and Th
> > requirements.
> > Regards,
> > Steve.
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-- D. C. Sessions [email protected]
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