From: [email protected]
Date: Thu Nov 04 1999 - 06:54:02 PST
David,
Most of the SSO analysis I have done has been on single-ended CMOS drivers
rather than differential, so take this with a grain of salt. My
understanding of how a "true" differential driver is supposed to work is
that the true and complement outputs are supposed to balance each other out
such that the net di/dt they draw from the rail is low, i.e. the true
output draws a positive di/dt while the complement output draws a negative
di/dt. This implies that somebody spent a lot of time optimizing the
output and predrive stages to insure a truly differential output (which, I
think, may be a hard thing to do in a CMOS process). Do you know if this
is the case? I know I've seen one case where a GTL driver was incorrectly
designed and produced high ringing during the turn-off transient. The
classic GTL driver has a bleeder circuit which is supposed to prevent this
from happening...
I would echo what D.C. said about the package model: to do an accurate SSO
analysis, you need a REALLY GOOD fully-coupled package model. It's not
necessary to have a huge one with 50 leads or anything. Start by breaking
the package down into the smallest repeating unit, as dictated by your
signal-to-return ratio. Incidentally, I would also use the most accurate
driver model you have, i.e. a structural (SPICE) model that is extracted
from the cell layout.
Happy hunting!
Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email protected]
---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
11/04/99 08:33 AM ---------------------------
David Haedge <[email protected]> on 11/03/99 12:46:07 PM
Please respond to [email protected]
To: [email protected]
cc:
Subject: [SI-LIST] : LVDS SSO Analysis Question
Fellow SIers,
I am working on an SSO analysis that involves large numbers of LVDS outputs
switching on a die. One of the reasons to use LVDS is because the driver
is
basically just redirecting a 4mA current in the output loop, hopefully
eliminating large di/dt's on power and ground. However, my SPICE analysis
shows a 20-25mA current spike on VDD and VSS with a rise/fall time of about
230ps each time the device switches (375MHz rate). It was assumed that we
could get by with a lot less VDD and VSS pads due to the expected low
di/dt's.
It appears now that with this large unexpected current spike, we need to
triple
the number of powers and grounds to achieve an acceptable voltage
drop/ground
bounce. Has anybody out there seen this sort of behavior in LVDS
circuitry?
Or is this just perhaps a quirk in SPICE (or my chosen vendor)?
Anxiously awaiting replies,
David Haedge
Raytheon
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