From: Istvan NOVAK (firstname.lastname@example.org)
Date: Wed Nov 03 1999 - 05:15:43 PST
Very good points, but let me add some clarifications.
It is true that a transient disturbance on the (bare) planes spreads
radially and its magnitude decays with the distance, similarly to a
radiowave propagating in free air. This is, however, true only in the
transient sense. For repetitive (periodical) excitation, resonances due to
the finite sizes do occur, unless the structure itself is lossy enough to
sufficiently suppress the resonances. The steady-state transfer impedance
profile may show impedance peaks, which are sometimes even bigger than the
impedance magnitude at the excitation point. Consequence: at a remote
point, the noise from a given source is bigger than at the source itself.
This effect was simulated and measured on various structures independently
by different people, and has been documented/published in several articles
at (among others) EPEP conferences and also in the IEEE Tr. CPMT August 1999
issue. Some of those articles are also available on-line.
The question also comes up whether these resonances occur and/or can be seen
in real products. Here the answer is: it depends on the design. That is
why those people whos designs inherently suppress or do not excite those
resonances may correctly state that have not seen these resonances in
practice. For instance, if the power-distribution network (for any reason)
uses lots of bypass capacitors connected to the planes, those capacitors may
sufficiently suppress the resonances. Similarly, if the board size is
small, the resonance peaks are shifted to higher frequencies, and at those
higher frequencies either there may not be sufficient steady-state energy
from the connected circuits to excite the resonances, or the damping from
the high-frequency losses of the buried capacitance does the job.
In some other opinions, the low resistance associated with he power
consumption of the silicon chips will suppress the resonances. While this
may be true, it may not be the safest design: this works OK only if the
fluctuation (transient) of the silicon's equivalent conductance is small
compared to its average conductance, otherwise the noise will be too big.
In other words, to keep the noise low, we need a power-distribution network
which looks like a wideband voltage source to the chips so that the
influance of the chips on the power-distribution network (including the
possible suppression of resonances by those chips) is minimal.
You should also be careful in evaluating measured results. For physically
small or lower-power designs a measurement resolution in the ohms range may
be sufficient, so the usual one-port impedance measurements with impedance
analyzers or vector network analyzers are OK. In these cases the
discontinuities in the measurement setup may add significant inductance to
the loop without raising the upper boundary of the measured impedances, but
the same connection inductance may mask out the resonance minima, showing a
smoother impedance profile. Such measurements may prove that the impedance
is below a given threshold (and the planes may do a perfect job in a design
where this requirement is sufficient), but this does not prove the absence
of resonances. For physically large and/or high-current designs, however,
the power-distribution-impedance requirement and the needed measurement
resolution may be in the milliohm range. One possible way to achieve such
measurement resolution was published at DesignCon99 (also available on
Again, the above statements are just clarifications and do not want to
question the usefulness of the buried capacitance layers.
----- Original Message -----
From: Dr. Edward P. Sayre <email@example.com>
To: <firstname.lastname@example.org>; <MikonCons@aol.com>
Sent: Tuesday, November 02, 1999 5:08 PM
Subject: Re: [SI-LIST] : Comment on Johnson's article (Now
> I can "resonate" with Mike Conn about the positive effects of buried
> capacitance layers.
> In the past, I didn't want to believe that they were as beneficial as they
> appear, having written about and investigated various types of bypass
> capacitor configurations through careful SPICE simulations and otherwise.
> The fact of the matter is the BC layers do a better job of delivering
> risetime currents to the chip power pins all other things being equal...
> However, remember that the return planes for the signal transmission lines
> must be have either well bypassed or low inductance connections to the BC
> layers as well so that the signal currents returns over direct and low
> parasitic (low series incremental inductance) paths back to the chip
> and power pins (in the case of CMOS driven x-mission lines with minimum of
> negative SI effects.
> ed sayre
> At 05:18 PM 11/1/99 EST, you wrote:
> >John: (RE: Self-resonance)
> >The buried capacitance (BC) configuration behaves as a (very) low
> >transmission line; hence, the phenomenon to consider/analyze is (as you
> >suspected) the propagation delay of perturbations between the planes.
> >that the magnitude of a disturbance caused by a sudden chip current
> >reduces rapidly with distance from the demand point as the required
> >drawn from a capacitor whose area is increasing at the square of the
> >which is increasing at the propagation speed through the dielectric.
> >though the board will still have an electrical resonance related to the
> >dimensions, the voltage perturbation reaching a given board edge is small
> >the radiation resistance of the closely spaced planes is beneficially
> >mismatched to that of free space (120xPI, or 377 ohms); hence reduced
> >will be radiated relative to other board constructions. The energy is
> >reflected back from the plane edges and continues to dissipate in the
> >In early 1993, boards using BC were tested over frequency by Zycon/Hadco
> >I repeated and confirmed the results in my lab). Other than the
> >external power supply leads with the large parallel-plate capacitor that
> >BC laminate creates, there were no high frequency resonances observable.
> >There may be some more up-to-date tests that Hadco and/or other using
> >have performed that may shed more light on this subject, but I have not
> >this particular item addressed in any technical notes. (Responses
> >BC does do a remarkable job of filtering power supply ripple and
> >frequencies from 40 MHz on up to the multiple GHz range. Since late
> >a consultant and presenter, I have advocated the use of BC for high
> >design in my own tutorials and recommended BC as a beneficial design tool
> >the 1993 HP High-Speed Digital Design Symposium (presented across the US
> >throughout Europe and parts of Asia). Today's high-speed systems can
> >strongly from use of this design technique.
> >Michael L. Conn
> >Owner/Principal Consultant
> >Mikon Consulting
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