From: Gregg Fokken (email@example.com)
Date: Tue Nov 02 1999 - 11:35:16 PST
I'm looking for information on CMOS PECL/LVPECL as well. I haven't found
much yet, but if I do, I'll forward you the information. Please return the
Thanks for the input. I was trying to figure out how folks were
implementing this without having Vgs (at Voh) that wasn't near cutoff. The
second rail for the source-followers makes a lot of sense for fixing the
problem on the IC, but obviously complicates the system design a bit. Out
of curiousity, is your 3.3V predriver still in the form of a differential
amplifier (like standard ECL) and if so, how do you go from single-ended
CMOS in the core to drive this? If not the same architecture as standard
ECL, what does this predriver look like? Or am I now also approaching the
point of needing an NDA... :-) Thanks in advance for any ideas you're
willing/able to share.
On Nov 2, 9:37am, D. C. Sessions wrote:
> Subject: Re: [SI-LIST] : PECL output buffer implementation in CMOS
> Jayarama Shenoy wrote:
> > Hi All,
> > Can someone provide insight into PECL output buffer
> > implementation in CMOS tecnologies? It is being claimed
> > that this cannot be done while at the same time retaining
> > the power supply noise rejection of differential output
> > drivers, which I find hard to understand.
> > Any pointers to public literature on PECL (or similar diff-
> > erential) output drivers in CMOS will be greatly appreciated.
> Hey, Jay.
> PECL can most certainly be done in CMOS. That, or the ones I'm
> shipping use previously-unknown laws of physics. As for telling
> YOU the details, you now need an NDA. Should've asked before you
> Seriously, what your sources were referring to was that since CMOS
> doesn't make efficient low-offset pullup followers the way bipolar
> does, you don't get the benefits of hanging the positive rail on
> the high-impedance collector (or drain) node of the transistor.
> The high impedance of the collector node means that voltage noise
> on the positive rail doesn't show up as current noice on the output.
> The hidden assumption here is that the CMOS output follower has to
> run on the same supply as the predriver. Where bipolar thrives on
> small base-emitter voltages, MOS devices need more voltage bias and
> the voltages available in PECL aren't well-chosen for this. (Duh!)
> On the other hand, nowhere is it written in stone that the positive
> rail for PECL has to be +5 volts. 2.5 volts with a 3.3 volt predriver
> gives an output common-mode point of about 1.2 volts, which is by
> astonishing coincidence also (a) centered in the rails, and (b) the
> common-mode point for LVDS. Astonishing. And along with this comes
> a high-state Vgs of 1.5 volts, which is enough to make a reasonable
> NMOS output device happy without desaturating it.
> Another possibility is to run open-drain. If you absolutely need the
> speed, this is nice because you don't have to coordinate the pullup
> an pulldown devices.
> The reference supply voltage for PECL is a system tradeoff. Personally,
> the more I work with PECL the more unprintable things I find to say
> about it. That acronym lends itself to some amazing abuse, let me
> tell you. If you have *anything* resembling a choice, run (don't walk)
> to a more sensible scheme like HSTL or GLVDS. A lot of the 'PECL'
> applications I'm seeing actually don't require PECL and would work fine
> with almost any low-swing differential scheme.
> D. C. Sessions
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>-- End of excerpt from D. C. Sessions
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