RE: [SI-LIST] : Comment on Johnson's article

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From: Chris Cheng (hycheng@3pardata.com)
Date: Mon Nov 01 1999 - 16:36:30 PST


larry,
   the fact that you see a 50-100MHz peak in power impedance proves
my point. the on die decoupling is taking care of the >100MHz noise
while there is a lower frequency resonance you need to take care of
outside the die. sure you can beef up the external decoupling with
higher resonance capacitors but the same 50-100MHz you observe will
go up due to lack of bulk charge. don't forget the discussion starts
with a finite among of decoupling capacitor that can be near the
silicon.
   while it is true that there are 50W CPU's to or above 500MHz,
anyone who have done power analysis on these puppies will know the
power profile for these chip will never ramp from 0-100% in a single
cycle. it is always a super-position of a slower multiple cycle ramp
and local instantanous highspeed spikes. the high speed spike can only
be taken care by on die decoupling. no decoupling cap in the world can
be placed close enough to the die to be effective at those frequency.
what you are shooting for is to take care of the slower multiple cycle
ramp using the most and bulkiest cap you can place need the die and
that's the origin of the 50-100MHz you observed in your power
distribution analysis.
   as for the image current return, i thought a while ago you posted
a message mentioning the image current return between power/ground
planes through the plane capacitance which i happen to agree fully.
the trick there is to ensure at least one of them is the source of
the original I/O current.
   chris

> Chris - I agree with you concerning the inductance of the package
> standing in between the PCB and the chip that is consuming the power.
> The on-chip decoupling capacitance and the package inductance forms a
> resonant circuit. For most of the projects that I have worked on in
> the last 10 years, that resonance has been between 50 and 100 MHz. The
> chip capacitance keeps going up and the package inductance keeps going
> down so that the product remains fairly constant. If we are just
> thinking in terms of supplying the core logic with clean power, then we
> don't need to decouple the PCB much above 100 MHz. We need charge
> stored on the package and/or chip to supply current above that frequency.
>
> However, a peak in the PCB power distribution impedance above 100 MHz
> can hurt us badly in terms of EMI. Sure, the package makes a nice low
> pass filter that tends to contain chip noise. But suppose we have 20
> dB of isolation from the chip to the PCB at 500 MHz. If we are
> consuming 50 watts of power at 500MHz (very possible with modern uP)
> then 5 watts make it to the PCB. We certainly do not want peaks in the
> power distribution system impedance that can be stimulated to resonance
> by some clock or harmonic.
>
> Also, the IO circuits depend upon the power planes to carry return
> current. Under some conditions, that return current must pass between
> the Vdd and Gnd power planes. With sub nSec rise times, we need low
> impedance between the Vdd and Gnd PCB power planes up to nearly 1 GHz.
> This is accomplished by discrete capacitors working together with
> power plane pairs (VDD and Gnd).
>
> regards,
> Larry Smith
> Sun Microsystems
>
>
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