From: Doug Brooks (firstname.lastname@example.org)
Date: Mon Nov 01 1999 - 09:59:27 PST
Perhaps you can explain it to him this way;
1. There is always stray inductance on a board, from a variety of sources
including sinply the traces themselves.
2. The noise voltage across an inductance is given by V = L * di/dt
3. High-speed designs are where this noise voltage becomes significant
enough to be an issue.
4. The noise voltage will increase as parasitic L increases and as di
increases, both of which don't really change much through the years.
5. The noise voltage increases as dt goes DOWN. dt has and does change
dramatically through the years. dt is the same thing as "rise time".
6. When you divide a small number (like parasitic inductance) by a REALLY
small number, like dt = 1 nanosecond --- 10(-9) --- what you get is a BIG
High speed designs are those where this type of noise ---caused by real
small rise times --- becomes an issue.
It is NOT a frequency issue, it is a RISE TIME issue. If you have a 1 MHz
frequency with a 10(-7) rise time you only have 1 percent of the high speed
design problem you have with a 1 MHz frequency with a 10(-9) rise time!
At 12:54 PM 11/1/99 +0800, you wrote:
>Pardon me for asking this stupid question because I am at a loss of how
>to explain hi-speed to my boss. He thinks that hi-speed is as simple and
>straightforward as resistance = V/I and nothing else. Hi-speed should be
>some circuits that need to operate at xxMHz or more. Anything less than
>xxMhz is not hi-speed.
>I would appreciate anyone of you experts out there who can enlighten me
>in a simple and easy to understand definition so that my boss can
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