[SI-LIST] : Parasitic Equivalent Circuits

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From: Abe Riazi (ariazi@anigma.com)
Date: Fri Oct 29 1999 - 19:43:50 PDT

Dear Scholars:

    There are many behavioral models having defective parasitic
sections, making it risky to employ any model in a SI simulation before
examining and verifying the accuracy of its parasitic parameters. When
analyzing parasitic effects, it is useful to consider equivalent
circuits of the pin and package parasitics. Some of these circuits are
quite simple. For example, the package parasitic of an IBIS model are
represented by a series R, series L, and parallel C. Even simpler is
the equivalent circuit for a XTK PIN statement which consists of a
series L and a shunt C, as R_pin is ignored.

     In some cases it is desirable to determine the equivalent circuit
for merged connector pins. For instance, the case of daughter board
with edge fingers which plug into a connector belonging to a
motherboard. If each finger of the daughter board and each pin of the
motherboard connector are represented by a series L and a shunt C, then
the equivalent circuit of the interfaced pins can be a pi LC circuit.
However, it should be added that high frequency simulations at times
require more complex equivalent circuit representations for each
individual pin and interconnects.

   The Single-Line-Model (SLM) and Multi-Line-Model (MLM) by AMP offer
an intriguing family of connector models. I have inspected SLM models
for NLX, PCI connectors and Slot 2. They contain equivalent circuits
for the lumped RLC and the distributed (including Zo and Tpd)
versions. It is then straight forward to create the Quad equivalents
for these connector models in various forms including the lumped, the
transmission line or the TOPSPEC formats. It is also easy to determine
the fastest acceptable edge rate by using the one tenth rule suggested
by AMP. It states that for optimum results, the propagation delay
should not exceed one tenth of the edge speed. For instance, if maximum
Tpd is 80 ps, then the fastest recommended transition speed is 800 ps.

   The model parasitics can noticeably influence the outcome of a
simulation. A quick method to observe parasitic effects is to compare
the waveforms at the pin and the pad (die) nodes of a device. It is
also noteworthy that signal quality (i.e. overshoot, undershoot,
ringback, etc.) are usually evaluated at the pad of the receiver,
whereas flight time is measured relative to the receiver and driver
pins. The term "flight time" should not be confused with "propagation
delay". These two terms are at times used interchangeably, although
they are different. Signal propagation delay represents the time
difference between when a signal leaves a driver pin and the time it
arrives at a receiver pin. Flight time is the time difference between
when a signal crosses a voltage threshold at the input pin of the
receiver, and the time output pin of the driver crosses a reference
voltage (Vref) were it driving a test load.

    In conclusion, to accurately create or validate behavioral models
or to correctly utilize them in a SI simulation demand an appreciation
for pin and package parasitic parameters. The equivalent parasitic
circuits, so valuable towards analysis of parasitic effects, are often
remarkably simple.

   With an appreciation for your comments and best regards,

   Abe Riazi
   Anigma, Inc.

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