Re: [SI-LIST] : quad offset stripline?

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From: Pat Zabinski (zabinski.patrick@mayo.edu)
Date: Thu Oct 28 1999 - 08:51:36 PDT


Bill,

We did consider this. By inserting a plane between S & Y, we
needed to either narrow the S & Y trace widths (higher fab cost)
or thicken the dielectric (i.e., outside the overall board
thickness spec) in order to maintain the same impedance. In
addition, the added plane itself added some thickness to
the board (i.e., we're sqeeze-in every mil in total height).
We even went to the extent of using lower Dk materials (~3.8-3.9)
over standard FR4 to push the board thickness down a tad-bit
more.

Thanks for double-checking, but when we looked at the details,
the quad-stripline stackup came in at slightly thinner.

Pat

On Oct 28, 10:20am, Bill Dempsey wrote:
> Subject: Re: [SI-LIST] : quad offset stripline?
> Pat,
>
> I have to ask a basic question. Why did you choose to do this vs.
inserting a 2 mil power core between layers S & Y? Realistically you can get
better route densities and you *don't* have to change the total stack height.
 And
> you've reduced a lot of problems out. Have you considered this?
>
> Regards,
>
> Bill D.
>
> Pat Zabinski wrote:
>
> > On a rather route-intense design we're working on, we are trying
> > to squeeze in as many signal layers as we possibly can in
> > a given overall board thickness. We've been playing around
> > with different scenarios with different board vendors for
> > the past month, and what we've come up with is a layer stackup
> > based on "quad offset stripline", meaning:
> >
> > ---------------------- plane
> > ---- signal-T
> > ---- signal-S
> > ---- signal-Y
> > ---- signal-X
> > ---------------------- plane
> >
> > X is horizontal, Y is vertical, S is 45, and T is 135. We have
> > buried vias between S & T and between X & Y. For a particular
> > signal, we only route on orthogonal layer-pairs.
> >
> > We've been analyzing this for a short time now, and it looks like
> > it might work out for our application. But before we take it too
> > far, I'd like to get input from folks on potential gotchas that
> > I should be concerned with.
> >
> > As background, we have:
> >
> > * designed a line width for the respective layers to obtain
> > our target impedance (50 ohms).
> >
> > * ran SSN eye diagram simulations of multiple signals
> > on one layer at a time to determine the minimum
> > trace-pitch for that layer.
> >
> > * using the minimum-pitch per layer, mutual capacitance
> > and inductance of the crossovers (taking into account
> > the relative angle of the traces), and a W-element
> > representation of lines on each of the four
> > layers, we ran an SSN eye diagram simulation of random
> > signals on all four layers to determine the effects
> > of the mutual parasitics from the other layers.
> >
> > So far, if we keep the trace pitch wide enough, this seems to
> > work just fine. However, I'd like input of other areas we
> > should look at.
> >
> > Any ideas? Has anyone used this sort of thing in the multi-100's
> > of MHz (<500 psec Tr) regime? Am I missing something?
> >
> > Thanks,
> > Pat
> >
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>-- End of excerpt from Bill Dempsey

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