From: Pat Zabinski (firstname.lastname@example.org)
Date: Thu Oct 28 1999 - 05:25:48 PDT
On a rather route-intense design we're working on, we are trying
to squeeze in as many signal layers as we possibly can in
a given overall board thickness. We've been playing around
with different scenarios with different board vendors for
the past month, and what we've come up with is a layer stackup
based on "quad offset stripline", meaning:
X is horizontal, Y is vertical, S is 45, and T is 135. We have
buried vias between S & T and between X & Y. For a particular
signal, we only route on orthogonal layer-pairs.
We've been analyzing this for a short time now, and it looks like
it might work out for our application. But before we take it too
far, I'd like to get input from folks on potential gotchas that
I should be concerned with.
As background, we have:
* designed a line width for the respective layers to obtain
our target impedance (50 ohms).
* ran SSN eye diagram simulations of multiple signals
on one layer at a time to determine the minimum
trace-pitch for that layer.
* using the minimum-pitch per layer, mutual capacitance
and inductance of the crossovers (taking into account
the relative angle of the traces), and a W-element
representation of lines on each of the four
layers, we ran an SSN eye diagram simulation of random
signals on all four layers to determine the effects
of the mutual parasitics from the other layers.
So far, if we keep the trace pitch wide enough, this seems to
work just fine. However, I'd like input of other areas we
should look at.
Any ideas? Has anyone used this sort of thing in the multi-100's
of MHz (<500 psec Tr) regime? Am I missing something?
**** To unsubscribe from si-list: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
This archive was generated by hypermail 2b29 : Tue Feb 29 2000 - 11:39:23 PST